linux.git/drivers/clk/meson, branch v4.20

clk: meson: axg: mark fdiv2 and fdiv3 as critical

2018-11-08T18:21:21+00:00

Similar to gxbb and gxl platforms, axg SCPI Cortex-M co-processor
uses the fdiv2 and fdiv3 to, among other things, provide the cpu
clock.

Until clock hand-off mechanism makes its way to CCF and the generic
SCPI claims platform specific clocks, these clocks must be marked as
critical to make sure they are never disabled when needed by the
co-processor.

Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
Signed-off-by: Jerome Brunet 
Acked-by: Neil Armstrong 
Signed-off-by: Stephen Boyd

clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL

2018-11-08T18:12:46+00:00

On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems
with reboot; e.g. a ~60 second delay between issuing reboot and the
board power cycling (and in some OS configurations reboot will fail
and require manual power cycling).

Similar to 'commit c987ac6f1f088663b6dad39281071aeb31d450a8 ("clk:
meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL")' the SCPI Cortex-M4
Co-Processor seems to depend on FCLK_DIV3 being operational.

Until commit 05f814402d6174369b3b29832cbb5eb5ed287059 ("clk:
meson: add fdiv clock gates"), this clock was modeled and left on by
the bootloader.

We don't have precise documentation about the SCPI Co-Processor and
its clock requirement so we are learning things the hard way.

Marking this clock as critical solves the problem but it should not
be viewed as final solution. Ideally, the SCPI driver should claim
these clocks. We also depends on some clock hand-off mechanism
making its way to CCF, to make sure the clock stays on between its
registration and the SCPI driver probe.

Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
Signed-off-by: Christian Hewitt 
Signed-off-by: Jerome Brunet 
Signed-off-by: Stephen Boyd

clk: meson: meson8b: use the regmap in the internal reset controller

2018-09-26T10:02:00+00:00

For now the reset controller was using raw register access because the
early init did not initialize the regmap. However, now that clocks are
initialized early we can simply use the regmap also for the reset
controller.
No functional changes.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson: meson8b: register the clock controller early

2018-09-26T10:02:00+00:00

Until now only the reset controller (part of the clock controller
register space) was registered early in the boot process, while the
clock controller itself was registered later on.
However, some parts of the SoC are initialized early in the boot process,
such as the SRAM and the TWD timer. The bootloader already enables these
clocks so we didn't see any issues so far.

Register the clock controller early so other drivers (such as the SRAM
and TWD timer) can use the clocks early in the boot process.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson-axg: pcie: drop the mpll3 clock parent

2018-09-26T10:02:00+00:00

We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.

Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin 
Signed-off-by: Yixun Lan 
Signed-off-by: Jerome Brunet

clk: meson: axg: round audio system master clocks down

2018-09-26T10:02:00+00:00

Some of the master clocks provided by the axg audio clock controller are
system clock (spdifin and pdm sysclk). They are used to clock an internal
DSP of the related devices. Having them constantly rounded down instead
of closest is preferable.

Signed-off-by: Jerome Brunet

clk: meson: clk-pll: drop hard-coded rates from pll tables

2018-09-26T10:02:00+00:00

Putting hard-coded rates inside the parameter tables assumes that
the parent is known and will never change. That's a big assumption
we should not make.

We have everything we need to recalculate the output rate using
the parent rate and the rest of the parameters. Let's do so and
drop the rates from the tables.

Acked-by: Neil Armstrong 
Reviewed-by: Martin Blumenstingl 
Tested-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson: clk-pll: remove od parameters

2018-09-26T10:01:57+00:00

Remove od parameters from pll clocks and add post dividers clocks
instead. Some clock, especially the one which feature several ods,
may provide output between those ods. Also, some drivers, such
as the hdmi driver, may require a more detailed control of the
clock dividers, compared to what CCF would perform automatically.

One added benefit of removing ods is that it also greatly reduce the
size of the rate parameter tables.

In the future, we could possibly take the predivider 'n' out of this
driver as well. To do so, we will need to understand the constraints
for the PLL to lock and whether or not it depends on the input clock
rate.

Acked-by: Neil Armstrong 
Reviewed-by: Martin Blumenstingl 
Tested-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary

2018-09-26T10:00:28+00:00

CLK_GET_RATE_NOCACHE should only be necessary when the registers
controlling the rate of clock may change outside of CCF. On Amlogic,
it should only be the case for the hdmi pll which is directly controlled
by the display driver (WIP to fix this).

The other plls should not require this flag.

Reviewed-by: Martin Blumenstingl 
Tested-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson: clk-pll: add enable bit

2018-09-26T10:00:28+00:00

Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.

Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements

Acked-by: Neil Armstrong 
Reviewed-by: Martin Blumenstingl 
Tested-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet