linux.git/drivers/clk/meson, branch v4.19

clk: meson: add gen_clk

2018-07-09T11:49:31+00:00

GEN_CLK is able to route several internal clocks to one of the SoC
pads. In the future, even more clocks could be made accessible using
cts_msr_clk - the clock measure block.

Signed-off-by: Jerome Brunet

clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition

2018-07-09T11:49:22+00:00

HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition

Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Acked-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson-axg: add clocks required by pcie driver

2018-07-09T11:49:11+00:00

Adding clocks for the pcie driver. Due to the ASIC design,
the pcie controller re-use part of the mipi clock logic,
so the mipi clock is also added.

Tested-by: Jianxin Qin 
Signed-off-by: Yixun Lan 
[amended to remove unnecessary locales]
Signed-off-by: Jerome Brunet

clk: meson: remove unused clk-audio-divider driver

2018-07-09T11:48:59+00:00

clk-audio-divider is no longer used, we can remove it.

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson: stop rate propagation for audio clocks

2018-07-09T11:48:59+00:00

It is actually a lot easier to setup the PLL with carefully chosen rates
than relying on CCF clock propagation for this audio use case.
This way, we can make sure we will always be able to provide the common
audio clock rates, while having the PLL in the optimal operating range.

For this, we stop the rate propagation at the mux picking the
PLL and let it round to the closest matching PLL.

Doing so, we can use the generic divider for the i2s clock.
clk-audio-divider is no longer required. It was a (poor) attempt
to use CCF rate propagation while making sure the PLL rate would
be high enough to work with audio use cases.

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson: axg: add the audio clock controller driver

2018-07-09T11:48:26+00:00

The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.

It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson: add axg audio sclk divider driver

2018-07-09T11:48:25+00:00

Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific features which make the generic
divider unsuitable to control it:
- zero based divider (div = val + 1), but zero value gates the clock,
  so minimum divider value is 2.
- lrclk variant may adjust the duty cycle depending the divider value
  and the 'hi' value.

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson: add triple phase clock driver

2018-07-09T11:47:22+00:00

Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control the phase provided to
the different element using the sample clock generator. This simplify
the usage of the sample clock generator a lot, without comprising the
ability of the SoC.

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson: add clk-phase clock driver

2018-07-09T11:47:22+00:00

Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson: clean-up meson clock configuration

2018-07-09T11:46:21+00:00

Clean the dependencies in meson clock Kconfig.
CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also,
each platform should select CLK_AMLOGIC, so everything is properly turned
on when the platform Kconfig enable each configuration flag

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet