linux.git/drivers/clk/meson, branch v4.16

clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()

2018-01-10T21:24:36+00:00

platform_get_resource() may return NULL, add proper
check to avoid potential NULL dereferencing.

This is detected by Coccinelle semantic patch.

@@
expression pdev, res, n, t, e, e1, e2;
@@

res = platform_get_resource(pdev, t, n);
+ if (!res)
+   return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);

Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

Merge tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson into clk-meson

2018-01-03T01:51:29+00:00

Pull Amlogic clk driver update from Jerome Brunet:

 - Fix overflow in the mpll driver on 32bits arch

* tag 'meson-clk-for-v4.16-3' of git://github.com/BayLibre/clk-meson:
  clk: meson: mpll: use 64-bit maths in params_from_rate

clk: meson-axg: make local symbol axg_gp0_params_table static

2017-12-28T18:42:07+00:00

Fixes the following sparse warning:

drivers/clk/meson/axg.c:260:25: warning:
 symbol 'axg_gp0_params_table' was not declared. Should it be static?

Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: meson-axg: fix return value check in axg_clkc_probe()

2017-12-28T18:42:05+00:00

In case of error, the function devm_ioremap() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.

Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Wei Yongjun 
Signed-off-by: Stephen Boyd

clk: meson: mpll: use 64-bit maths in params_from_rate

2017-12-23T22:14:20+00:00

"rem * SDM_DEN" can easily overflow on the 32-bit Meson8 and Meson8b
SoCs if the "remainder" (after the division operation) is greater than
262143Hz. This is likely to happen since the input clock for the MPLLs
on Meson8 and Meson8b is "fixed_pll", which is running at a rate of
2550MHz.

One example where this was observed to be problematic was the Ethernet
clock calculation (which takes MPLL2 as input). When requesting a rate
of 125MHz there is a remainder of 2500000Hz.
The resulting MPLL2 rate before this patch was 127488329Hz.
The resulting MPLL2 rate after this patch is 124999103Hz.

Commit b609338b26f5 ("clk: meson: mpll: use 64bit math in
rate_from_params") already fixed a similar issue in rate_from_params.

Fixes: 007e6e5c5f01d3 ("clk: meson: mpll: add rw operation")
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson-axg: add clock controller drivers

2017-12-14T09:19:37+00:00

Add clock controller drivers for Amlogic Meson-AXG SoC.

Acked-by: Neil Armstrong 
Signed-off-by: Qiufang Dai 
Signed-off-by: Yixun Lan 
Signed-off-by: Jerome Brunet

clk: meson: make the spinlock naming more specific

2017-12-14T09:12:41+00:00

Make the spinlock more specific, so better for lockdep
debugging and ctags/grep.

Suggested-by: Stephen Boyd 
Signed-off-by: Yixun Lan 
Signed-off-by: Jerome Brunet

clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks

2017-12-08T20:37:19+00:00

Remove CLK_IGNORE_UNUSED from mmc clocks. This was only needed while the
mmc driver incorrectly used the xtal as source instead of the mmc
clock. Now, the driver takes the correct clock, CCF is aware that the
clock is being used and we can remove this flag.

Signed-off-by: Jerome Brunet 
Acked-by: Kevin Hilman

clk: meson: gxbb: fix wrong clock for SARADC/SANA

2017-11-27T13:33:38+00:00

According to the datasheet, in Meson-GXBB/GXL series,
The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].

Test passed at gxl-s905x-p212 board.

The following published datasheets are wrong and should be updated
[1] GXBB v1.1.4
[2] GXL v0.3_20170314

Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Tested-by: Xingyu Chen 
Signed-off-by: Yixun Lan 
Signed-off-by: Jerome Brunet

clk: meson: gxbb: Add VPU and VAPB clocks data

2017-10-20T08:34:49+00:00

The Amlogic Meson GX SoCs needs these two clocks to power up the
VPU power domain.

These two clocks are similar to the MALI clocks by having a glitch-free
mux and two similar clocks with gate, divider and muxes.

Acked-by: Jerome Brunet 
[narmstrong: removed the CLK_IGNORE_UNUSED on muxes and dividers]
Signed-off-by: Neil Armstrong