linux.git/drivers/clk/meson, branch v4.14

Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into clk-next

2017-08-23T22:28:52+00:00

Pull Amlogic clock driver updates from Neil Armstrong:

 * meson8b: add the reset controller to the clkc
 * meson: expose all clk ids
 * gxbb-aoclk: Add CEC 32k clock
 * gxbb: add mmc input 0 clocks
 * meson: fix protection against undefined clks
 * gxbb: fix audio divider flags

* tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson:
  clk: meson: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb-aoclk: Switch to regmap for register access
  dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings
  clk: meson: gxbb: Add sd_emmc clk0 clocks
  clk: meson: gxbb: fix clk_mclk_i958 divider flags
  clk: meson: gxbb: fix meson cts_amclk divider flags
  clk: meson: meson8b: register the built-in reset controller
  dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb: Add sd_emmc clk0 clkids
  clk: meson-gxbb: expose almost every clock in the bindings
  clk: meson8b: expose every clock in the bindings
  clk: meson: gxbb: fix protection against undefined clks
  clk: meson: meson8b: fix protection against undefined clks
  dt-bindings: clock: meson8b: describe the embedded reset controller

clk: meson: gxbb-aoclk: Add CEC 32k clock

2017-08-04T16:02:02+00:00

The CEC 32K AO Clock is a dual divider with dual counter to provide a more
precise 32768Hz clock for the CEC subsystem from the external xtal.

Signed-off-by: Neil Armstrong

clk: meson: gxbb-aoclk: Switch to regmap for register access

2017-08-04T16:02:01+00:00

Switch the aoclk driver to use the new bindings and switch all the
registers access to regmap only.

Signed-off-by: Neil Armstrong

clk: meson: gxbb: Add sd_emmc clk0 clocks

2017-08-04T16:02:00+00:00

Input source 0 of the mmc controllers is not directly xtal, as currently
described in DT. Each controller is fed by a composite clock (the usual
mux, divider and gate). The muxes inputs are the xtal (default) and the
fclk_div clocks. These parents, along with the divider, should be able to
provide the necessary rates for mmc and nand operation.

The input muxes should also be able to take mpll2, mpll3 and gp0_pll but
these are precious clocks, needed for other usage. It is better if the
mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is
not listed among the possible parents.

Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong

clk: meson: gxbb: fix clk_mclk_i958 divider flags

2017-08-04T16:01:59+00:00

CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags
while it should have been in the divider flags

Fixes: 3c277c247eab ("clk: meson: gxbb: add cts_mclk_i958")
Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong

clk: meson: gxbb: fix meson cts_amclk divider flags

2017-08-04T16:01:59+00:00

CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags
while it should have been in the divider flags

Fixes: 4087bd4b2170 ("clk: meson: gxbb: add cts_amclk")
Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong

clk: meson: meson8b: register the built-in reset controller

2017-08-04T16:01:58+00:00

The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).

According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET

All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.

Suggested-by: Carlo Caione 
Signed-off-by: Martin Blumenstingl 
Reviewed-by: Neil Armstrong 
Signed-off-by: Neil Armstrong

clk: meson: gxbb: Add sd_emmc clk0 clkids

2017-08-04T15:49:34+00:00

Add the clkids for the clocks feeding the input0 of the mmc controllers

Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong

clk: meson-gxbb: expose almost every clock in the bindings

2017-08-04T15:49:33+00:00

Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed

Acked-by: Neil Armstrong 
Acked-by: Arnd Bergmann 
Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong

clk: meson8b: expose every clock in the bindings

2017-08-04T15:49:33+00:00

Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed (none on this
particular controller at the moment)

Acked-by: Neil Armstrong 
Acked-by: Arnd Bergmann 
Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong