linux.git/drivers/clk/meson, branch v4.13

clk: meson: mpll: fix mpll0 fractional part ignored

2017-08-01T12:18:31+00:00

mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet 
Signed-off-by: Neil Armstrong

Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next

2017-06-16T22:01:46+00:00

Pull Amlogic clk driver updates from Jerome Brunet:

 * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
 * Add new compatible to the meson8 clock controller for meson8b
 * Add missing parents to gxbb clk81

* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
  clk: meson: gxbb: add all clk81 parents
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  clk: meson8b: export the ethernet gate clock
  clk: meson8b: export the USB clocks
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the SAR ADC clocks

clk: meson: gxbb: add all clk81 parents

2017-06-16T18:51:42+00:00

Remove the FIXME on clk81 mux and add all the documented parents

Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

Merge branch 'next/headers' into next/drivers

2017-06-16T18:32:36+00:00

clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

2017-06-12T07:33:08+00:00

The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.

Signed-off-by: Martin Blumenstingl 
Acked-by: Rob Herring 
Acked-by: Kevin Hilman 
Signed-off-by: Jerome Brunet

clk: meson8b: export the ethernet gate clock

2017-06-12T07:30:45+00:00

Export the ethernet gate clock to the dt-bindings.

Signed-off-by: Martin Blumenstingl 
Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson8b: export the USB clocks

2017-06-12T07:30:44+00:00

Export the USB related clocks (for the USB controller and the USB2 PHYs)
so they can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl 
Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson8b: export the gate clock for the HW random number generator

2017-06-12T07:30:43+00:00

This exports the clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl 
Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson8b: export the SDIO clock

2017-06-12T07:30:42+00:00

Export the SDIO clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl 
Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet

clk: meson8b: export the SAR ADC clocks

2017-06-12T07:30:41+00:00

Export the clocks for the SAR ADC so they can be used in the
dt-bindings.

Signed-off-by: Martin Blumenstingl 
Acked-by: Neil Armstrong 
Signed-off-by: Jerome Brunet