linux.git/drivers/clk/meson, branch v4.12

clk: meson: gxbb: fix build error without RESET_CONTROLLER

2017-05-16T09:05:01+00:00

With CONFIG_RESET_CONTROLLER=n we see the following link error in the
meson gxbb clk driver:

drivers/built-in.o: In function 'gxbb_aoclkc_probe':
drivers/clk/meson/gxbb-aoclk.c:161: undefined reference to 'devm_reset_controller_register'

Fix this by selecting the reset controller subsystem.

Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Signed-off-by: Tobias Regnery 
Acked-by: Neil Armstrong 
[narmstrong: Added fixes-by tag]
Signed-off-by: Neil Armstrong

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2017-05-10T20:38:18+00:00

Pull clk updates from Stephen Boyd:
 "Sort of on the quieter side this time, which is probably due more to
  me not catching up as quickly on patch review than anything else.
  Overall it seems normal though, a few small changes to the core,
  mostly small non-critical fixes here and there as well as driver
  updates for new and existing hardware support.

  The biggest things are the TI clk driver rework to lay the groundwork
  for clkctrl support in the next merge window and the AmLogic
  audio/graphics clk support.

  Core:
   - clk_possible_parents debugfs file so we know which parents a clk
     could possibly have
   - Fix to make clk rate change notifiers stop on the first failure
     instead of continuing

  New Drivers:
   - Mediatek MT6797 SoCs
   - hi655x PMIC clks
   - AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
   - Allwinner H5 SoCs and PRCM hardware

  Updates:
   - Nvidia Tegra T210 cleanups and non-critical fixes
   - TI OMAP cleanups in preparation for clkctrl support
   - trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
   - ZTE zx296718 SoC VGA clks
   - Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
   - IDT VersaClock 5P49V5935 support
   - Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
     support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
  clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
  clk: ti: divider: try to fix ti_clk_register_divider
  clk: mvebu: Use kcalloc() in two functions
  clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
  clk: nomadik: Delete error messages for a failed memory allocation in two functions
  clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
  clk: Improve a size determination in two functions
  clk: Replace four seq_printf() calls by seq_putc()
  clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
  clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
  clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
  reset: mediatek: Add MT2701 ethsys reset controller include file
  clk: mediatek: add mt2701 ethernet reset
  clk: hi6220: Add the hi655x's pmic clock
  clk: ti: fix building without legacy omap3
  clk: ti: fix linker error with !SOC_OMAP4
  clk: hi3620: Fix a typo in one variable name
  clk: hi3620: Delete error messages for a failed memory allocation in two functions
  clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
  clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
  ...

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2017-05-09T17:07:33+00:00

Pull ARM 64-bit DT updates from Olof Johansson:
 "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
  of smaller changes, but also some new platforms that are worth
  mentioning:

   - Rockchip RK3399 platforms for Chromebooks, including Samsung
     Chromebook Plus (Kevin)

   - Orange Pi PC2 (Allwinner H5)

   - Freescale LS2088A and LS1088A SoCs

   - Expanded support for Nvidia Tegra186 (and Jetson TX2)"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
  arm64: dts: Add basic DT to support Spreadtrum's SP9860G
  arm64: dts: exynos: Use - instead of @ for DT OPP entries
  arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
  arm64: dts: juno: add information about L1 and L2 caches
  arm64: dts: juno: fix few unit address format warnings
  arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
  arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
  arm64: marvell: dts: add crypto engine description for 7k/8k
  arm64: dts: marvell: add sdhci support for Armada 7K/8K
  arm64: dts: marvell: add eMMC support for Armada 37xx
  arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
  arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
  arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
  arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
  dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
  ...

clk: meson: mpll: use 64bit math in rate_from_params

2017-04-07T15:45:30+00:00

On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz.
Multiplying this with SDM_DEN results in a value greater than 32bits.
This is not a problem on the 64bit Meson GX SoCs, but it may result in
undefined behavior on the older 32bit Meson8b SoC.

While rate_from_params was only introduced recently to make the math
reusable from _round_rate and _recalc_rate the original bug exists much
longer.

Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong 
Signed-off-by: Martin Blumenstingl 
[as discussed on the ml, use DIV_ROUND_UP_ULL]
Signed-off-by: Jerome Brunet

clk: meson: mpll: fix division by zero in rate_from_params

2017-04-07T15:45:21+00:00

According to the public datasheet all register bits in HHI_MPLL_CNTL7,
HHI_MPLL_CNTL8 and HHI_MPLL_CNTL9 default to zero. On all GX SoCs these
seem to be initialized by the bootloader to some default value.
However, on my Meson8 board they are not initialized, leading to a
division by zero in rate_from_params as the math is:
(parent_rate * SDM_DEN) / ((SDM_DEN * 0) + 0)

According to the datasheet, the minimum n2 value is 4. The rate provided
by the clock when n2 is less than this minimum is unpredictable. In such
case, we report an error.

Although the rate_from_params function was only introduced recently the
original bug has been there for much longer. It was only exposed
recently when the MPLL clocks were added to the Meson8b clock driver.

Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong 
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet

clk: meson: gxbb: add cts_i958 clock

2017-04-07T14:50:46+00:00

This adds the cts_i958 clock to control the clock source of the spdif
output block. This mux is not explicitly mentionned in the documentation
but it is critical to the spdif dai. It is used to select whether the clock
source of the spdif output is cts_amclk (when data are taken from i2s
buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer)

Acked-by: Michael Turquette 
Signed-off-by: Jerome Brunet

clk: meson: gxbb: add cts_mclk_i958

2017-04-07T14:50:46+00:00

Add the spdif master clock also referred as cts_mclk_i958

Acked-by: Michael Turquette 
Signed-off-by: Jerome Brunet

clk: meson: gxbb: add cts_amclk

2017-04-07T14:50:45+00:00

Add the i2s master clock also referred as cts_amclk

Acked-by: Michael Turquette 
Signed-off-by: Jerome Brunet

clk: meson: add audio clock divider support

2017-04-07T14:50:44+00:00

The audio divider needs a specific clock divider driver.
With am mpll parent clock, which is able to provide a fairly precise rate,
the generic divider tends to select low value of the divider. In such case
the quality of the clock is very poor. For the same final rate, maximizing
the audio clock divider value and selecting the corresponding mpll rate
gives better results. This is what this driver aims to acheive. So far, so
good.

Cc: Hendrik v. Raven 
Acked-by: Michael Turquette 
Signed-off-by: Jerome Brunet

clk: meson: gxbb: protect against holes in the onecell_data array

2017-04-07T14:50:44+00:00

The clock controller is getting more complex and it might be possible, in
the future, to have holes in the clk_hw_onecell_data array. Just make sure
we skip those holes if it ever happens.

Acked-by: Michael Turquette 
Signed-off-by: Jerome Brunet