<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/clk/meson, branch v4.11</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2017-03-04T00:15:48+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2017-03-04T00:15:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a1a0db36d8c89243d989186108fe9196ad0e2c2d'/>
<id>a1a0db36d8c89243d989186108fe9196ad0e2c2d</id>
<content type='text'>
Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

  This includes two branches for arm64 dt updates, both following up on
  earlier changes for the same platforms that are already merged:

  Samsung:
   - add USB3 support in Exynos7
   - minor PM related updates

  Amlogic:
   - new machines: WeTek Set-top-boxes
   - various devices added to DT

  There are also a couple of bugfixes that trickled in since the start
  of the merge window:

   - The moxart_defconfig was not building the intended platform
   - CPU-hotplug was broken on ux500
   - Coresight was broken on Juno (never worked)"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  ARM: deconfig: fix the moxart defconfig
  ARM: ux500: resume the second core properly
  arm64: dts: juno: update definition for programmable replicator
  arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
  arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
  arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
  pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
  arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
  ARM64: dts: meson-gxbb-p200: add ADC laddered keys
  ARM64: dts: meson: meson-gx: add the SAR ADC
  ARM64: dts: meson-gxl: add the pwm_ao_b pin
  ARM64: dts: meson-gx: add the missing pwm_AO_ab node
  clk: gxbb: fix CLKID_ETH defined twice
  ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
  clk: gxbb: add the SAR ADC clocks and expose them
  dt-bindings: amlogic: Add WeTek boards
  ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
  dt-bindings: vendor-prefix: Add wetek vendor prefix
  ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
  ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

  This includes two branches for arm64 dt updates, both following up on
  earlier changes for the same platforms that are already merged:

  Samsung:
   - add USB3 support in Exynos7
   - minor PM related updates

  Amlogic:
   - new machines: WeTek Set-top-boxes
   - various devices added to DT

  There are also a couple of bugfixes that trickled in since the start
  of the merge window:

   - The moxart_defconfig was not building the intended platform
   - CPU-hotplug was broken on ux500
   - Coresight was broken on Juno (never worked)"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  ARM: deconfig: fix the moxart defconfig
  ARM: ux500: resume the second core properly
  arm64: dts: juno: update definition for programmable replicator
  arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost
  arm64: dts: exynos: Add USB 3.0 controller node for Exynos7
  arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7
  pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions
  arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
  ARM64: dts: meson-gxbb-p200: add ADC laddered keys
  ARM64: dts: meson: meson-gx: add the SAR ADC
  ARM64: dts: meson-gxl: add the pwm_ao_b pin
  ARM64: dts: meson-gx: add the missing pwm_AO_ab node
  clk: gxbb: fix CLKID_ETH defined twice
  ARM64: dts: meson-gxl: rename Nexbox A95x for consistency
  clk: gxbb: add the SAR ADC clocks and expose them
  dt-bindings: amlogic: Add WeTek boards
  ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play
  dt-bindings: vendor-prefix: Add wetek vendor prefix
  ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency
  ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: gxbb: fix CLKID_ETH defined twice</title>
<updated>2017-01-27T18:56:57+00:00</updated>
<author>
<name>jbrunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2017-01-26T16:05:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2d3b74d3836901c8601e147b1ae24170f9fa2982'/>
<id>2d3b74d3836901c8601e147b1ae24170f9fa2982</id>
<content type='text'>
CLKID_ETH is define in the dt-bindings but has not be commented out in the
clock driver. Just do it now.

Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
CLKID_ETH is define in the dt-bindings but has not be commented out in the
clock driver. Just do it now.

Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: meson8b: fix clk81 register address</title>
<updated>2017-01-26T23:54:48+00:00</updated>
<author>
<name>Jerome Brunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2017-01-25T10:53:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=340a84ce1eddd6671ce0c57d890fd90f6ae27fa2'/>
<id>340a84ce1eddd6671ce0c57d890fd90f6ae27fa2</id>
<content type='text'>
During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.

As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.

Fixed by just removing the second fixup.

Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.

As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.

Fixed by just removing the second fixup.

Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: gxbb: add the SAR ADC clocks and expose them</title>
<updated>2017-01-23T18:18:21+00:00</updated>
<author>
<name>Martin Blumenstingl</name>
<email>martin.blumenstingl@googlemail.com</email>
</author>
<published>2017-01-19T14:58:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=33d0fcdfe0e87070d96c678e554d711ae15b9fa6'/>
<id>33d0fcdfe0e87070d96c678e554d711ae15b9fa6</id>
<content type='text'>
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
  2-bit wide, but the datasheet only lists the parents for the first
  bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock

Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).

Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Tested-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
  2-bit wide, but the datasheet only lists the parents for the first
  bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock

Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).

Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Tested-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: meson-gxbb: Export HDMI clocks</title>
<updated>2017-01-18T18:17:53+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2017-01-17T12:08:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5a582cff47c90af29ecb293caa2f667bd4d45e54'/>
<id>5a582cff47c90af29ecb293caa2f667bd4d45e54</id>
<content type='text'>
Export HDMI clock from internal to dt-bindings.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Export HDMI clock from internal to dt-bindings.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2016-10-08T04:34:49+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2016-10-08T04:34:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c913fc4146ba7c280e074558d0a461e5c6f07c8a'/>
<id>c913fc4146ba7c280e074558d0a461e5c6f07c8a</id>
<content type='text'>
Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

   - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an
     automotive SoC similar to the ⅹ8a7795 chip we already support, but
     the dts changes rely on a clock driver change that has been merged
     for v4.9 through the clk tree.

   - The Amlogic meson-gxbb (S905) platform gains support for a few
     drivers merged through our tree, in particular the network and usb
     driver changes are required and included here, and also the clk
     tree changes.

   - The Allwinner platforms have seen a large-scale change to their clk
     drivers and the dts file updates must come after that. This
     includes the newly added Nextthing GR8 platform, which is derived
     from sun5i/A13.

   - Some integrator (arm32) changes rely on clk driver changes.

   - A single patch for lpc32xx has no such dependency but wasn't added
     until just before the merge window"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  ARM: dts: lpc32xx: add device node for IRAM on-chip memory
  ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03
  ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
  ARM: dts: sun8i: add pinmux for UART1 at PG
  dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
  dts: sun8i-h3: add pinmux definitions for I2C0-2
  dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
  dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
  dts: sun8i-h3: add pinmux definitions for UART2-3
  ARM: dts: sun9i: a80-optimus: Disable EHCI1
  ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused
  ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused
  ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h
  ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

   - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an
     automotive SoC similar to the ⅹ8a7795 chip we already support, but
     the dts changes rely on a clock driver change that has been merged
     for v4.9 through the clk tree.

   - The Amlogic meson-gxbb (S905) platform gains support for a few
     drivers merged through our tree, in particular the network and usb
     driver changes are required and included here, and also the clk
     tree changes.

   - The Allwinner platforms have seen a large-scale change to their clk
     drivers and the dts file updates must come after that. This
     includes the newly added Nextthing GR8 platform, which is derived
     from sun5i/A13.

   - Some integrator (arm32) changes rely on clk driver changes.

   - A single patch for lpc32xx has no such dependency but wasn't added
     until just before the merge window"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  ARM: dts: lpc32xx: add device node for IRAM on-chip memory
  ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03
  ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
  ARM: dts: sun8i: add pinmux for UART1 at PG
  dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
  dts: sun8i-h3: add pinmux definitions for I2C0-2
  dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
  dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
  dts: sun8i-h3: add pinmux definitions for UART2-3
  ARM: dts: sun9i: a80-optimus: Disable EHCI1
  ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused
  ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused
  ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h
  ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: gxbb: expose i2c clocks</title>
<updated>2016-09-14T18:24:04+00:00</updated>
<author>
<name>Jerome Brunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2016-09-14T10:06:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=dfdd7d4af6ebee027be7bf2636b2314937948da6'/>
<id>dfdd7d4af6ebee027be7bf2636b2314937948da6</id>
<content type='text'>
I2C and AO_I2C clocks are needed for the i2c driver, expose to DT
(and comment out in clk driver)

Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
I2C and AO_I2C clocks are needed for the i2c driver, expose to DT
(and comment out in clk driver)

Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: gxbb: expose USB clocks</title>
<updated>2016-09-14T18:23:55+00:00</updated>
<author>
<name>Martin Blumenstingl</name>
<email>martin.blumenstingl@googlemail.com</email>
</author>
<published>2016-09-04T21:31:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5dbe7890e6e998b49aac3f0a6455803c956a49c9'/>
<id>5dbe7890e6e998b49aac3f0a6455803c956a49c9</id>
<content type='text'>
USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related
dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs.
Expose these clocks to DT and comment out in clk driver.

Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related
dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs.
Expose these clocks to DT and comment out in clk driver.

Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: gxbb: expose spifc clock</title>
<updated>2016-09-14T18:22:49+00:00</updated>
<author>
<name>Jerome Brunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2016-09-07T15:13:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f2120a8b090676380d9bce4ea23f855dc8e0d71f'/>
<id>f2120a8b090676380d9bce4ea23f855dc8e0d71f</id>
<content type='text'>
SPI clock is needed for the spifc driver, expose to DT
(and comment out in the clk driver)

Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
SPI clock is needed for the spifc driver, expose to DT
(and comment out in the clk driver)

Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: gxbb: expose MPLL2 clock for use by DT</title>
<updated>2016-09-14T18:22:49+00:00</updated>
<author>
<name>Martin Blumenstingl</name>
<email>martin.blumenstingl@googlemail.com</email>
</author>
<published>2016-09-06T21:38:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ed6f4b518004845f6f830422cc9e3ab4f0284930'/>
<id>ed6f4b518004845f6f830422cc9e3ab4f0284930</id>
<content type='text'>
This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.

Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.

Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
</pre>
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