linux.git/drivers/clk/meson/Kconfig, branch vsnprintf

clk: amlogic: axg-audio: revert reset implementation

2024-12-03T01:21:03+00:00

The audio subsystem of axg based platform is not probing anymore.
This is due to the introduction of RESET_MESON_AUX and the config
not being enabled with the default arm64 defconfig.

This brought another discussion around proper decoupling between
the clock and reset part. While this discussion gets sorted out,
revert back to the initial implementation.

This reverts
 * commit 681ed497d676 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX")
 * commit 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver")

Both are reverted with single change to avoid creating more compilation
problems.

Fixes: 681ed497d676 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX")
Cc: Arnd Bergmann 
Reported-by: Mark Brown 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20241128-clk-audio-fix-rst-missing-v2-1-cf437d1a73da@baylibre.com
Signed-off-by: Stephen Boyd

clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX

2024-11-14T20:33:10+00:00

As in most cases, using 'imply' is wrong here and does not prevent
build failures since that code may not be visible to a built-in
clk driver:

axg-audio.c:(.text+0x15c): undefined reference to `devm_meson_rst_aux_register'

Replace the incorrt 'imply' with the necessary 'depends on'.

Fixes: 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver")
Signed-off-by: Arnd Bergmann 
Link: https://lore.kernel.org/r/20241111102932.3209861-1-arnd@kernel.org
Reviewed-by: Jerome Brunet 
Signed-off-by: Stephen Boyd

clk: amlogic: axg-audio: use the auxiliary reset driver

2024-10-14T08:11:05+00:00

Remove the implementation of the reset driver in axg audio
clock driver and migrate to the one provided by the reset framework
on the auxiliary bus

Reviewed-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20241008-meson-clk-rst-aux-v2-1-682ab9151f4f@baylibre.com
Signed-off-by: Jerome Brunet

clk: meson: c3: add c3 clock peripherals controller driver

2024-06-04T08:38:32+00:00

Add the C3 peripherals clock controller driver in the C3 SoC family.

[jbrunet: fix Kconfig select order and probe function name]
Co-developed-by: Chuan Liu 
Signed-off-by: Chuan Liu 
Signed-off-by: Xianwei Zhao 
Link: https://lore.kernel.org/r/20240522082727.3029656-6-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet

clk: meson: c3: add support for the C3 SoC PLL clock

2024-06-04T08:38:16+00:00

Add the C3 PLL clock controller driver for the Amlogic C3 SoC family.

[jbrunet: fixed probe function name]
Co-developed-by: Chuan Liu 
Signed-off-by: Chuan Liu 
Signed-off-by: Xianwei Zhao 
Link: https://lore.kernel.org/r/20240522082727.3029656-5-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet

clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF

2024-04-10T07:46:21+00:00

In order to setup the DSI clock, let's make the unused VCLK2 clock path
configuration via CCF.

The nocache option is removed from following clocks:
- vclk2_sel
- vclk2_input
- vclk2_div
- vclk2
- vclk_div1
- vclk2_div2_en
- vclk2_div4_en
- vclk2_div6_en
- vclk2_div12_en
- vclk2_div2
- vclk2_div4
- vclk2_div6
- vclk2_div12
- cts_encl_sel

vclk2 and vclk2_div uses the newly introduced vclk regmap driver
to handle the enable and reset bits.

In order to set a rate on cts_encl via the vclk2 clock path,
the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order
to keep CCF from selection a parent.
The parents of cts_encl_sel & vclk2_sel are expected to be defined
in DT or manually set by the display driver at some point.

The following clock scheme is to be used for DSI:

xtal
\_ gp0_pll_dco
   \_ gp0_pll
      |- vclk2_sel
      |  \_ vclk2_input
      |     \_ vclk2_div
      |        \_ vclk2
      |           \_ vclk2_div1
      |              \_ cts_encl_sel
      |                 \_ cts_encl	-> to VPU LCD Encoder
      |- mipi_dsi_pxclk_sel
      \_ mipi_dsi_pxclk_div
         \_ mipi_dsi_pxclk		-> to DSI controller

The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table
in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input.

The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the
DSI bitclock is the reference base clock to calculate the vclk2_div value
when pixel clock is set on the cts_encl endpoint.

Signed-off-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-3-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet

clk: meson: add vclk driver

2024-04-10T07:46:21+00:00

The VCLK and VCLK_DIV clocks have supplementary bits.

The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.

The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated with CLK_SET_RATE_GATE it ensures
the rate is set while the divider is disabled and in reset mode.

The VCLK_DIV enable bit isn't implemented as a gate since it's part
of the divider logic and vendor does this exact sequence to ensure
the divider is correctly set.

Signed-off-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet

clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS

2023-10-23T12:54:35+00:00

Without this, the newly added drivers fail to link:

aarch64-linux-ld: drivers/clk/meson/s4-pll.o: in function `meson_s4_pll_probe':
s4-pll.c:(.text+0x13c): undefined reference to `meson_clk_hw_get'
aarch64-linux-ld: drivers/clk/meson/s4-peripherals.o: in function `meson_s4_periphs_probe':
s4-peripherals.c:(.text+0xb0): undefined reference to `meson_clk_hw_get'

Fixes: e787c9c55eda ("clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver")
Reviewed-by: Jerome Brunet 
Reviewed-by: Neil Armstrong 
Signed-off-by: Arnd Bergmann 
Link: https://lore.kernel.org/r/20231023102810.4001943-1-arnd@kernel.org
[jbrunet: use 12 char for the Fixes as recommended ]
Signed-off-by: Jerome Brunet

clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller

2023-09-27T09:01:03+00:00

Add the peripherals clock controller driver in the S4 SoC family.

[jbrunet: remove extra new line at end of s4-peripherals.h]
Signed-off-by: Yu Tu 
Link: https://lore.kernel.org/r/20230904075504.23263-5-yu.tu@amlogic.com
Signed-off-by: Jerome Brunet

clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

2023-09-27T08:54:24+00:00

Add the S4 PLL clock controller driver in the S4 SoC family.

Signed-off-by: Yu Tu 
Link: https://lore.kernel.org/r/20230904075504.23263-4-yu.tu@amlogic.com
Signed-off-by: Jerome Brunet