linux.git/drivers/clk/mediatek, branch v6.9

clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port

2024-04-11T03:50:26+00:00

Due to what seems to be an undocumented oddity in MediaTek's MT7988
SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.

This currently leads to PCIe port 2 not working in Linux.

Reflect the apparent relationship in the clk driver to make sure PCIe
port 2 of the MT7988 SoC works.

Fixes: 4b4719437d85f ("clk: mediatek: add drivers for MT7988 SoC")
Suggested-by: Sam Shih 
Signed-off-by: Daniel Golle 
Link: https://lore.kernel.org/r/1da2506a51f970706bf4ec9509dd04e0471065e5.1710367453.git.daniel@makrotopia.org
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Stephen Boyd

clk: mediatek: Do a runtime PM get on controllers during probe

2024-04-11T03:50:06+00:00

mt8183-mfgcfg has a mutual dependency with genpd during the probing
stage, which leads to a deadlock in the following call stack:

CPU0:  genpd_lock --> clk_prepare_lock
genpd_power_off_work_fn()
 genpd_lock()
 generic_pm_domain::power_off()
    clk_unprepare()
      clk_prepare_lock()

CPU1: clk_prepare_lock --> genpd_lock
clk_register()
  __clk_core_init()
    clk_prepare_lock()
    clk_pm_runtime_get()
      genpd_lock()

Do a runtime PM get at the probe function to make sure clk_register()
won't acquire the genpd lock. Instead of only modifying mt8183-mfgcfg,
do this on all mediatek clock controller probings because we don't
believe this would cause any regression.

Verified on MT8183 and MT8192 Chromebooks.

Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
Signed-off-by: Pin-yen Lin 

Link: https://lore.kernel.org/r/20240312115249.3341654-1-treapking@chromium.org
Reviewed-by: AngeloGioacchino Del Regno 
Tested-by: AngeloGioacchino Del Regno 
Signed-off-by: Stephen Boyd

clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe()

2024-02-29T01:13:53+00:00

Add a label so that a bit of exception handling can be better reused
at the end of this function implementation.

Signed-off-by: Markus Elfring 
Link: https://lore.kernel.org/r/6a64e7b3-b1ce-46c4-9c85-89f731aee592@web.de
Reviewed-by: AngeloGiaocchino Del Regno 
Signed-off-by: Stephen Boyd

clk: mediatek: add infracfg reset controller for mt7988

2024-02-22T05:03:17+00:00

Infracfg can also operate as reset controller, add support for it.

Signed-off-by: Frank Wunderlich 
Reviewed-by: AngeloGioacchino Del Regno 
Link: https://lore.kernel.org/r/20240201182409.39878-3-linux@fw-web.de
Signed-off-by: Stephen Boyd

clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical

2024-02-22T04:55:50+00:00

Without the SGM_REG_SEL clock enabled the cpu freezes if trying to
access registers used by MT7981 clock drivers itself.
Mark SGM_REG_SEL as critical to make sure it is always enabled to
prevent freezes on boot even if the Ethernet driver which prepares
and enables the clock is not loaded or probed at a later point.

Fixes: 813c3b53b55b ("clk: mediatek: add MT7981 clock support")
Signed-off-by: Daniel Golle 
Link: https://lore.kernel.org/r/fc157139e6b7f8dfb6430ac7191ba754027705e8.1708221995.git.daniel@makrotopia.org
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Stephen Boyd

clk: mediatek: mt8183: Correct parent of CLK_INFRA_SSPM_32K_SELF

2024-02-22T04:55:30+00:00

CLK_INFRA_SSPM_32K_SELF has the "f_f26m_ck" clock assigned as its parent.
This is inconsistent as the clock is part of a group that are all gates
without dividers, and this makes the kernel think it runs at 26 MHz.

After clarification from MediaTek engineers, the correct parent is
actually the system 32 KHz clock.

Fixes: 1eb8d61ac5c9 ("clk: mediatek: mt8183: Add back SSPM related clocks")
Signed-off-by: Chen-Yu Tsai 
Link: https://lore.kernel.org/r/20240219105125.956278-1-wenst@chromium.org
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Stephen Boyd

clk: mediatek: mt7622-apmixedsys: Fix an error handling path in clk_mt8135_apmixed_probe()

2024-02-22T04:51:57+00:00

'clk_data' is allocated with mtk_devm_alloc_clk_data(). So calling
mtk_free_clk_data() explicitly in the remove function would lead to a
double-free.

Remove the redundant call.

Fixes: c50e2ea6507b ("clk: mediatek: mt7622-apmixedsys: Add .remove() callback for module build")
Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/2c553c2a5077757e4f7af0bb895acc43881cf62c.1704616152.git.christophe.jaillet@wanadoo.fr
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Stephen Boyd

clk: mediatek: mt8135: Fix an error handling path in clk_mt8135_apmixed_probe()

2024-02-22T04:51:33+00:00

If an error occurs after mtk_alloc_clk_data(), mtk_free_clk_data() should
be called, as already done in the remove function.

Fixes: 54b7026f011e ("clk: mediatek: mt8135-apmixedsys: Convert to platform_driver and module")
Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/6cd6af61e5a91598068227f1f68cfcfde1507453.1704615011.git.christophe.jaillet@wanadoo.fr
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Stephen Boyd

clk: mediatek: add drivers for MT7988 SoC

2024-01-03T23:57:02+00:00

Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
typical MediaTek designs.

Also add driver for XFIPLL clock generating the 156.25MHz clock for
the XFI SerDes. It needs an undocumented software workaround and has
an unknown internal design.

Signed-off-by: Sam Shih 
Signed-off-by: Daniel Golle 
Reviewed-by: AngeloGioacchino Del Regno 
Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
[sboyd@kernel.org: Add module license to infracfg file]
Signed-off-by: Stephen Boyd

clk: mediatek: add pcw_chg_bit control for PLLs of MT7988

2024-01-03T23:55:19+00:00

Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
of the previously hardcoded PCW_CHG_MASK macro if set.
This will needed for clocks on the MT7988 SoC.

Signed-off-by: Sam Shih 
Signed-off-by: Daniel Golle 
Reviewed-by: AngeloGioacchino Del Regno 
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd