linux.git/drivers/clk/mediatek, branch v5.16 Linux kernel source tree clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c 2021-11-02T22:27:21+00:00 Ran Jianping ran.jianping@zte.com.cn 2021-10-19T06:29:39+00:00 59d9bcbfddb921f0469515c93c3a05ea0fb9dc83 'dt-bindings/clock/mt8195-clk.h' included in '/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c' is duplicated.It is also included on the 13 line. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Ran Jianping <ran.jianping@zte.com.cn> Link: https://lore.kernel.org/r/20211019062939.979660-1-ran.jianping@zte.com.cn Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
'dt-bindings/clock/mt8195-clk.h' included in
'/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c' is duplicated.It is
also included on the 13 line.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Ran Jianping <ran.jianping@zte.com.cn>
Link: https://lore.kernel.org/r/20211019062939.979660-1-ran.jianping@zte.com.cn
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Export clk_ops structures to modules 2021-09-15T01:57:23+00:00 Stephen Boyd sboyd@kernel.org 2021-09-15T01:52:40+00:00 a8cd038cac0d5572312015c3512aa1113fa6bbd4 modpost complains once these drivers become modules. ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined! Let's just export them. Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Cc: Miles Chen <miles.chen@mediatek.com> Fixes: 32b028fb1d09 ("clk: mediatek: support COMMON_CLK_MEDIATEK module build") Link: https://lore.kernel.org/r/20210915015540.1732014-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
modpost complains once these drivers become modules.

 ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined!

Let's just export them.

Cc: Hanks Chen <hanks.chen@mediatek.com>
Cc: Wendell Lin <wendell.lin@mediatek.com>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Miles Chen <miles.chen@mediatek.com>
Fixes: 32b028fb1d09 ("clk: mediatek: support COMMON_CLK_MEDIATEK module build")
Link: https://lore.kernel.org/r/20210915015540.1732014-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: support COMMON_CLK_MT6779 module build 2021-09-15T01:20:21+00:00 Miles Chen miles.chen@mediatek.com 2021-09-01T22:25:26+00:00 f09b9460a5e448dac8fb4f645828c0668144f9e6 To support COMMON_CLK_MT6779* module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210901222526.31065-4-miles.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
To support COMMON_CLK_MT6779* module build,
add MODULE_LICENSE and export necessary symbols.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Hanks Chen <hanks.chen@mediatek.com>
Cc: Wendell Lin <wendell.lin@mediatek.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210901222526.31065-4-miles.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: support COMMON_CLK_MEDIATEK module build 2021-09-15T01:20:20+00:00 Miles Chen miles.chen@mediatek.com 2021-09-01T22:25:25+00:00 32b028fb1d09a0e8353c1b4fae324d8c740aa05f To support COMMON_CLK_MEDIATEK module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210901222526.31065-3-miles.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
To support COMMON_CLK_MEDIATEK module build,
add MODULE_LICENSE and export necessary symbols.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Hanks Chen <hanks.chen@mediatek.com>
Cc: Wendell Lin <wendell.lin@mediatek.com>
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210901222526.31065-3-miles.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8195 apusys clock support 2021-09-14T22:05:39+00:00 Chun-Jie Chen chun-jie.chen@mediatek.com 2021-09-14T02:16:33+00:00 74e1652ce9d3a0155a07cf06360e680c36195742 Add MT8195 apusys clock controller which provides PLLs in AI processor Unit. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-25-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add MT8195 apusys clock controller which provides PLLs
in AI processor Unit.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-25-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8195 imp i2c wrapper clock support 2021-09-14T22:05:39+00:00 Chun-Jie Chen chun-jie.chen@mediatek.com 2021-09-14T02:16:32+00:00 222e0fbcef882e5f2707314a410680fb8eb2083e Add MT8195 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-24-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add MT8195 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-24-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8195 wpesys clock support 2021-09-14T22:05:39+00:00 Chun-Jie Chen chun-jie.chen@mediatek.com 2021-09-14T02:16:31+00:00 993e9a77e27f731ebf7395caf15284341d50c743 Add MT8195 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-23-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add MT8195 wpesys clock controllers which provide clock gate
control in Wrapping Engine.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-23-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8195 vppsys1 clock support 2021-09-14T22:05:39+00:00 Chun-Jie Chen chun-jie.chen@mediatek.com 2021-09-14T02:16:30+00:00 50df7722688593131da6dcd8caeda1c6cb989fcb Add MT8195 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-22-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add MT8195 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-22-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8195 vppsys0 clock support 2021-09-14T22:05:39+00:00 Chun-Jie Chen chun-jie.chen@mediatek.com 2021-09-14T02:16:29+00:00 f5bf0c1b486f908b3ff1736121cd65b0791796ec Add MT8195 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-21-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add MT8195 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-21-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: mediatek: Add MT8195 vencsys clock support 2021-09-14T22:05:39+00:00 Chun-Jie Chen chun-jie.chen@mediatek.com 2021-09-14T02:16:28+00:00 b5d728d8f1387352b354fa53b83c324618b29ba8 Add MT8195 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-20-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add MT8195 vencsys clock controllers which provide clock gate
control for video encoder.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-20-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>