<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/clk/mediatek, branch v4.13</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>clk: mediatek: export cpu multiplexer clock for MT8173 SoCs</title>
<updated>2017-06-20T02:02:44+00:00</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2017-05-05T15:26:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=567bf2ed86d13aecfb7d3c1ab75166193ce37213'/>
<id>567bf2ed86d13aecfb7d3c1ab75166193ce37213</id>
<content type='text'>
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs</title>
<updated>2017-06-20T02:02:44+00:00</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2017-05-05T15:26:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=43ed50ee5a181fcfbdeb7566f5e8122bad182889'/>
<id>43ed50ee5a181fcfbdeb7566f5e8122bad182889</id>
<content type='text'>
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work</title>
<updated>2017-06-20T02:02:43+00:00</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2017-05-05T15:26:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1e17de9049da5ef482ec8f6a875a83bec96bed3e'/>
<id>1e17de9049da5ef482ec8f6a875a83bec96bed3e</id>
<content type='text'>
This patch adds CPU multiplexer clocks which are essential for Mediatek
cpufreq driver. It would use the CPU clock multiplexer to switch to the
intermediate clock source temporarily and then wait for the primary clock
changing getting stable.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds CPU multiplexer clocks which are essential for Mediatek
cpufreq driver. It would use the CPU clock multiplexer to switch to the
intermediate clock source temporarily and then wait for the primary clock
changing getting stable.

Signed-off-by: Pi-Cheng Chen &lt;pi-cheng.chen@linaro.org&gt;
Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: add mt2701 ethernet reset</title>
<updated>2017-04-22T02:20:33+00:00</updated>
<author>
<name>John Crispin</name>
<email>john@phrozen.org</email>
</author>
<published>2017-01-23T12:48:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=db9c4a1e6581e45976526eb45c032a73f944dd8a'/>
<id>db9c4a1e6581e45976526eb45c032a73f944dd8a</id>
<content type='text'>
The ethernet clock core has a reset register that is currently not exposed
to the user. Fix this by adding the missing registration code.

Signed-off-by: John Crispin &lt;john@phrozen.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The ethernet clock core has a reset register that is currently not exposed
to the user. Fix this by adding the missing registration code.

Signed-off-by: John Crispin &lt;john@phrozen.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: add clk support for MT6797</title>
<updated>2017-04-19T16:20:21+00:00</updated>
<author>
<name>Kevin-CW Chen</name>
<email>kevin-cw.chen@mediatek.com</email>
</author>
<published>2017-04-08T01:20:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=96596aa06628e86ea0e1c08c34b0ccc7619e43ac'/>
<id>96596aa06628e86ea0e1c08c34b0ccc7619e43ac</id>
<content type='text'>
Add MT6797 clock support, include topckgen, apmixedsys, infracfg
and subsystem clocks

Signed-off-by: Kevin-CW Chen &lt;kevin-cw.chen@mediatek.com&gt;
Signed-off-by: Mars Cheng &lt;mars.cheng@mediatek.com&gt;
Tested-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add MT6797 clock support, include topckgen, apmixedsys, infracfg
and subsystem clocks

Signed-off-by: Kevin-CW Chen &lt;kevin-cw.chen@mediatek.com&gt;
Signed-off-by: Mars Cheng &lt;mars.cheng@mediatek.com&gt;
Tested-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Fix MT8135 dependencies</title>
<updated>2017-01-27T00:04:31+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2017-01-24T12:09:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3d21a4b6462aa2578192705b7b1eb4d40054d531'/>
<id>3d21a4b6462aa2578192705b7b1eb4d40054d531</id>
<content type='text'>
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber &lt;afaerber@suse.de&gt;
Acked-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber &lt;afaerber@suse.de&gt;
Acked-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Fix MT2701 dependencies</title>
<updated>2017-01-27T00:04:15+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2017-01-24T12:07:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6e9c0d5a3347047891936821d18d28903192468c'/>
<id>6e9c0d5a3347047891936821d18d28903192468c</id>
<content type='text'>
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.

Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: Andreas Färber &lt;afaerber@suse.de&gt;
Reviewed-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.

Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: Andreas Färber &lt;afaerber@suse.de&gt;
Reviewed-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: mediatek: Add MT2701 reset driver</title>
<updated>2016-11-08T23:59:51+00:00</updated>
<author>
<name>Shunli Wang</name>
<email>shunli.wang@mediatek.com</email>
</author>
<published>2016-11-04T07:43:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8c1ee96a2febee5a1dfb0e9d96c8f28a98f0a16b'/>
<id>8c1ee96a2febee5a1dfb0e9d96c8f28a98f0a16b</id>
<content type='text'>
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT2701 clock support</title>
<updated>2016-11-08T23:59:49+00:00</updated>
<author>
<name>Shunli Wang</name>
<email>shunli.wang@mediatek.com</email>
</author>
<published>2016-11-04T07:43:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e9862118272aa528e35e54ef9f1e35c217870fd7'/>
<id>e9862118272aa528e35e54ef9f1e35c217870fd7</id>
<content type='text'>
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Add hardware dependency</title>
<updated>2016-10-17T22:22:26+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2016-10-14T12:44:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=234d511d8c158d62f73f1a818eb4dd494a13a6e3'/>
<id>234d511d8c158d62f73f1a818eb4dd494a13a6e3</id>
<content type='text'>
Only propose the mediatek clock drivers on this platform, unless
build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Only propose the mediatek clock drivers on this platform, unless
build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
