<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/clk/mediatek, branch v4.11</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>clk: mediatek: Fix MT8135 dependencies</title>
<updated>2017-01-27T00:04:31+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2017-01-24T12:09:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3d21a4b6462aa2578192705b7b1eb4d40054d531'/>
<id>3d21a4b6462aa2578192705b7b1eb4d40054d531</id>
<content type='text'>
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber &lt;afaerber@suse.de&gt;
Acked-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber &lt;afaerber@suse.de&gt;
Acked-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Fix MT2701 dependencies</title>
<updated>2017-01-27T00:04:15+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2017-01-24T12:07:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6e9c0d5a3347047891936821d18d28903192468c'/>
<id>6e9c0d5a3347047891936821d18d28903192468c</id>
<content type='text'>
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.

Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: Andreas Färber &lt;afaerber@suse.de&gt;
Reviewed-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.

Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: Andreas Färber &lt;afaerber@suse.de&gt;
Reviewed-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>reset: mediatek: Add MT2701 reset driver</title>
<updated>2016-11-08T23:59:51+00:00</updated>
<author>
<name>Shunli Wang</name>
<email>shunli.wang@mediatek.com</email>
</author>
<published>2016-11-04T07:43:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8c1ee96a2febee5a1dfb0e9d96c8f28a98f0a16b'/>
<id>8c1ee96a2febee5a1dfb0e9d96c8f28a98f0a16b</id>
<content type='text'>
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT2701 clock support</title>
<updated>2016-11-08T23:59:49+00:00</updated>
<author>
<name>Shunli Wang</name>
<email>shunli.wang@mediatek.com</email>
</author>
<published>2016-11-04T07:43:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e9862118272aa528e35e54ef9f1e35c217870fd7'/>
<id>e9862118272aa528e35e54ef9f1e35c217870fd7</id>
<content type='text'>
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Add hardware dependency</title>
<updated>2016-10-17T22:22:26+00:00</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2016-10-14T12:44:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=234d511d8c158d62f73f1a818eb4dd494a13a6e3'/>
<id>234d511d8c158d62f73f1a818eb4dd494a13a6e3</id>
<content type='text'>
Only propose the mediatek clock drivers on this platform, unless
build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Only propose the mediatek clock drivers on this platform, unless
build-testing.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Cc: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Cc: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Cc: Erin Lo &lt;erin.lo@mediatek.com&gt;
Cc: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: clk-mt8173: Unmap region obtained by of_iomap</title>
<updated>2016-09-21T08:06:07+00:00</updated>
<author>
<name>Arvind Yadav</name>
<email>arvind.yadav.cs@gmail.com</email>
</author>
<published>2016-09-20T08:30:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=af9083627b4764272a341902e37af17188bc17f0'/>
<id>af9083627b4764272a341902e37af17188bc17f0</id>
<content type='text'>
Free memory mapping if init is not successful.

Signed-off-by: Arvind Yadav &lt;arvind.yadav.cs@gmail.com&gt;
Reviewed-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Free memory mapping if init is not successful.

Signed-off-by: Arvind Yadav &lt;arvind.yadav.cs@gmail.com&gt;
Reviewed-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Refine the makefile to support multiple clock drivers</title>
<updated>2016-08-19T19:18:38+00:00</updated>
<author>
<name>James Liao</name>
<email>jamesjj.liao@mediatek.com</email>
</author>
<published>2016-08-19T05:34:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2886c84681c4a10a8fecdea58bf749af09406a33'/>
<id>2886c84681c4a10a8fecdea58bf749af09406a33</id>
<content type='text'>
Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.

Signed-off-by: Shunli Wang &lt;shunli.wang@mediatek.com&gt;
Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Tested-by: John Crispin &lt;blogic@openwrt.org&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: remove __init from clk registration functions</title>
<updated>2016-08-19T00:15:30+00:00</updated>
<author>
<name>James Liao</name>
<email>jamesjj.liao@mediatek.com</email>
</author>
<published>2016-08-16T07:30:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=928f3bfb81e81e7f3ce6d37857a1ae075475678d'/>
<id>928f3bfb81e81e7f3ce6d37857a1ae075475678d</id>
<content type='text'>
Remove __init from functions that will be used by init functions
that support probe deferral.

Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove __init from functions that will be used by init functions
that support probe deferral.

Signed-off-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Signed-off-by: Erin Lo &lt;erin.lo@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: remove hdmitx_dig_cts from TOP clocks</title>
<updated>2016-05-06T15:47:42+00:00</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2016-01-04T17:36:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ac4b1280319c3032787ac95bfeff14a425c417bf'/>
<id>ac4b1280319c3032787ac95bfeff14a425c417bf</id>
<content type='text'>
The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output</title>
<updated>2016-05-06T15:47:40+00:00</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2015-11-30T21:07:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=4585945bf1d348d006f7270beea3dae09fee3413'/>
<id>4585945bf1d348d006f7270beea3dae09fee3413</id>
<content type='text'>
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
