linux.git/drivers/clk/keystone, branch v3.13

clk: keystone: Build Keystone clock drivers

2013-10-08T01:16:37+00:00

Now build the keystone common clock drivers. The build is made
conditional based on COMMON_CLK_KEYSTONE

Signed-off-by: Santosh Shilimkar 
Signed-off-by: Mike Turquette

clk: keystone: Add gate control clock driver

2013-10-08T01:16:30+00:00

Add the driver for the clock gate control which uses PSC (Power Sleep
Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and
disabling of the clocks for different IPs present in the SoC.

Signed-off-by: Santosh Shilimkar 
Signed-off-by: Mike Turquette

clk: keystone: add Keystone PLL clock driver

2013-10-08T01:16:21+00:00

Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.

Signed-off-by: Santosh Shilimkar 
Signed-off-by: Mike Turquette