linux.git/drivers/clk/imx, branch v6.16

clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data

2025-06-20T00:32:40+00:00

When num_parents is 4, __clk_register() occurs an out-of-bounds
when accessing parent_names member. Use ARRAY_SIZE() instead of
hardcode number here.

 BUG: KASAN: global-out-of-bounds in __clk_register+0x1844/0x20d8
 Read of size 8 at addr ffff800086988e78 by task kworker/u24:3/59
  Hardware name: NXP i.MX95 19X19 board (DT)
  Workqueue: events_unbound deferred_probe_work_func
  Call trace:
    dump_backtrace+0x94/0xec
    show_stack+0x18/0x24
    dump_stack_lvl+0x8c/0xcc
    print_report+0x398/0x5fc
    kasan_report+0xd4/0x114
    __asan_report_load8_noabort+0x20/0x2c
    __clk_register+0x1844/0x20d8
    clk_hw_register+0x44/0x110
    __clk_hw_register_mux+0x284/0x3a8
    imx95_bc_probe+0x4f4/0xa70

Fixes: 5224b189462f ("clk: imx: add i.MX95 BLK CTL clk driver")
Cc: stable@vger.kernel.org
Reviewed-by: Frank Li 
Signed-off-by: Xiaolei Wang 
Link: https://lore.kernel.org/r/20250619062108.2016511-1-xiaolei.wang@windriver.com
Signed-off-by: Stephen Boyd

clk: imx8mp: inform CCF of maximum frequency of clocks

2025-03-03T17:02:15+00:00

The IMX8MPCEC datasheet lists maximum frequencies allowed for different
modules. Some of these limits are universal, but some depend on
whether the SoC is operating in nominal or in overdrive mode.

The imx8mp.dtsi currently assumes overdrive mode and configures some
clocks in accordance with this. Boards wishing to make use of nominal
mode will need to override some of the clock rates manually.

As operating the clocks outside of their allowed range can lead to
difficult to debug issues, it makes sense to register the maximum rates
allowed in the driver, so the CCF can take them into account.

Reviewed-by: Peng Fan 
Signed-off-by: Ahmad Fatoum 
Link: https://lore.kernel.org/r/20250218-imx8m-clk-v4-6-b7697dc2dcd0@pengutronix.de
Signed-off-by: Abel Vesa

clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents

2025-03-03T16:49:45+00:00

The DSP and OCRAM_A modules from AUDIOMIX are clocked by
AUDIO_AXI_CLK_ROOT, not AUDIO_AHB_CLK_ROOT. Update the clock data
accordingly.

Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control")
Signed-off-by: Laurentiu Mihalcea 
Reviewed-by: Iuliana Prodan 
Reviewed-by: Peng Fan 
Link: https://lore.kernel.org/r/20250226164513.33822-3-laurentiumihalcea111@gmail.com
Signed-off-by: Abel Vesa

Merge branch 'clk-fixes' into clk-next

2025-01-21T19:22:46+00:00

* clk-fixes:
  clk: clk-loongson2: Fix the number count of clk provider
  clk: mmp2: call pm_genpd_init() only after genpd.name is set
  clk: sunxi-ng: a100: enable MMC clock reparenting
  clk: clk-imx8mp-audiomix: fix function signature
  clk: thead: Fix TH1520 emmc and shdci clock rate

clk: imx: Apply some clks only for i.MX93

2024-12-26T14:46:03+00:00

Enable the LVDS gate, MIPI DSI, PXP, FLEXIO and MU only for i.MX93,
because i.MX91 does not support them.

Update enet clk entry format to align with others.

Fixes: a27bfff88dd2 ("clk: imx: add i.MX91 clk")
Signed-off-by: Peng Fan 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20241225001443.883131-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa

clk: imx93: Add IMX93_CLK_SPDIF_IPG clock

2024-12-26T14:41:34+00:00

Split IMX93_CLK_SPDIF_IPG from IMX93_CLK_SPDIF_GATE
because the IMX93_CLK_SPDIF_GATE controls the gate
of IPG clock and root clock. Without this change,
disabling IMX93_CLK_SPDIF_GATE would also disable
the IPG clock, causing register access failures.

Fixes: 1c4a4f7362fd ("arm64: dts: imx93: Add audio device nodes")
Signed-off-by: Shengjiu Wang 
Reviewed-by: Frank Li 
Link: https://lore.kernel.org/r/20241119015805.3840606-3-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa

clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x

2024-12-26T14:28:18+00:00

The PLL1416x is used to implement SYS_PLL3 on i.MX8MP and can be used
to drive CLKOUTn clock. Add 208 MHz and 416 MHz entries to the PLL so
they can be generated by the PLL and used to produce e.g. 13 MHz or
26 MHz on CLKOUTn output.

Signed-off-by: Marek Vasut 
Reviewed-by: Peng Fan 
Link: https://lore.kernel.org/r/20241112013805.333798-1-marex@denx.de
Signed-off-by: Abel Vesa

clk: imx8mp: Fix clkout1/2 support

2024-12-26T14:27:44+00:00

The CLKOUTn may be fed from PLL1/2/3, but the PLL1/2/3 has to be enabled
first by setting PLL_CLKE bit 11 in CCM_ANALOG_SYS_PLLn_GEN_CTRL register.
The CCM_ANALOG_SYS_PLLn_GEN_CTRL bit 11 is modeled by plln_out clock. Fix
the clock tree and place the clkout1/2 under plln_sel instead of plain plln
to let the clock subsystem correctly control the bit 11 and enable the PLL
in case the CLKOUTn is supplied by PLL1/2/3.

Fixes: 43896f56b59e ("clk: imx8mp: add clkout1/2 support")
Signed-off-by: Marek Vasut 
Reviewed-by: Peng Fan 
Link: https://lore.kernel.org/r/20241112013718.333771-1-marex@denx.de
Signed-off-by: Abel Vesa

clk: clk-imx8mp-audiomix: fix function signature

2024-12-20T23:43:41+00:00

clk_imx8mp_audiomix_reset_controller_register() in the
"if !CONFIG_RESET_CONTROLLER" branch had the first
argument missing. It is an empty function for this branch
so it wasn't immediately apparent.

Fixes: 6f0e817175c5 ("clk: imx: clk-audiomix: Add reset controller")
Cc:  # 6.12.x
Signed-off-by: Nikolaus Voss 
Link: https://lore.kernel.org/r/20241219105447.889CB11FE@mail.steuer-voss.de
Reviewed-by: Daniel Baluta 
Acked-by: Shengjiu Wang 
Reviewed-by: Peng Fan 
Signed-off-by: Stephen Boyd

clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()

2024-11-05T10:07:59+00:00

If device_link_add() fails, it returns NULL pointer not ERR_PTR(),
replace IS_ERR() with NULL pointer check, and return -EINVAL.

Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver")
Signed-off-by: Yang Yingliang 
Reviewed-by: Peng Fan 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20241026112452.1523-1-yangyingliang@huaweicloud.com
Signed-off-by: Abel Vesa