linux.git/drivers/clk/imx, branch v5.8

clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice

2020-05-21T14:37:48+00:00

Switch the bus clk use imx8m_clk_hw_composite_bus, then
we could avoid possible issue when setting mux of the clk.

Signed-off-by: Peng Fan 
Reviewed-by: Dong Aisheng 
Signed-off-by: Shawn Guo

clk: imx: add imx8m_clk_hw_composite_bus

2020-05-21T14:37:48+00:00

Introduce imx8m_clk_hw_composite_bus api for bus clk root slice usage.
Because the mux switch sequence issue, we could not reuse Peripheral
Clock Slice code, need use composite specific mux operation.

Signed-off-by: Peng Fan 
Reviewed-by: Dong Aisheng 
Signed-off-by: Shawn Guo

clk: imx: add mux ops for i.MX8M composite clk

2020-05-21T14:37:48+00:00

The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].

It support target(smart) interface and normal interface. Target interface
is exported for programmer easy to configure ccm root. Normal interface
is also exported, but we not use it in our driver, because it will
introduce more complexity compared with target interface.

The normal interface simplified as below:
            SEL_A  GA
            +--+  +-+
            |  +->+ +------+
CLK[0-7]--->+  |  +-+      |
       |    |  |      +----v---+    +----+
       |    +--+      |pre_diva+---->    |  +---------+
       |              +--------+    |mux +--+post_div |
       |    +--+      |pre_divb+--->+    |  +---------+
       |    |  |      +----^---+    +----+
       +--->+  |  +-+      |
            |  +->+ +------+
            +--+  +-+
            SEL_B  GB

The mux in the upper pic is not the target interface MUX, target
interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7],
you are actually writing SEL_A or SEL_B depends on the internal
counter which will also control the internal "mux".

The target interface simplified as below which is used by Linux Kernel:
CLK[0-7]--->MUX-->Gate-->pre_div-->post_div

A requirement of the Target Interface's software is that the
target clock source is active, it means when setting SEL_A, the
current input clk to SEL_A must be active, same to SEL_B.

We touch target interface, but hardware logic actually also need
configure normal interface.

There will be system hang, when doing the following steps:
The initial state:
  SEL_A/SEL_B are both sourcing from clk0, the internal counter
  choose SEL_A.
1. switch mux from clk0 to clk1
   The hardware logic will choose SEL_B and configure SEL_B to clk1.
   SEL_A no changed.
2. gate off clk0
   Disable clk0, then the input to SEL_A is off.
3. swtich from clk1 to clk2
   The hardware logic will choose SEL_A and configure SEL_A to clk2,
   however the current SEL_A input clk0 is off, the system hang.

The solution to fix the issue is in step 1, write twice to
target interface MUX, it will make SEL_A/SEL_B both sources
from clk1, then no need to care about the state of clk0. And
finally system performs well.

Signed-off-by: Peng Fan 
Reviewed-by: Dong Aisheng 
Signed-off-by: Shawn Guo

clk: imx8m: migrate A53 clk root to use composite core

2020-05-20T01:27:04+00:00

Migrate A53 clk root to use composite core clk type. It
will simplify code and make it easy to use composite
specific mux operation.

Reviewed-by: Leonard Crestez 
Signed-off-by: Peng Fan 
Reviewed-by: Dong Aisheng 
Signed-off-by: Shawn Guo

clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code

2020-05-20T01:26:48+00:00

Use imx8m_clk_hw_composite_core to simpliy clks that belong to
core clk slice.

Reviewed-by: Leonard Crestez 
Signed-off-by: Peng Fan 
Reviewed-by: Dong Aisheng 
Signed-off-by: Shawn Guo

clk: imx8mp: Define gates for pll1/2 fixed dividers

2020-05-20T01:26:45+00:00

Inspried from
commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")

On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Reviewed-by: Dong Aisheng 
Reviewed-by: Leonard Crestez 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

clk: imx: imx8mp: fix pll mux bit

2020-05-20T01:26:42+00:00

Same to i.MX8MN/i.MX8MM, pll BYPASS bit should be kept inside pll
driver for glitchless freq setting following spec. If exposing the
bit, that means pll driver and clk driver has two paths to touch
this bit, which is wrong.

So use EXT_BYPASS bit here.

Reviewed-by: Dong Aisheng 
Reviewed-by: Leonard Crestez 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

clk: imx8m: drop clk_hw_set_parent for A53

2020-05-20T01:26:28+00:00

The parent settings have been moved to dtsi, we no need to
set parent here. And clk_hw_set_parent will trigger lockdep warning,
because this api not have prepare_lock.

Reported-by: Leonard Crestez 
Reviewed-by: Dong Aisheng 
Reviewed-by: Leonard Crestez 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

clk: imx: Add helpers for passing the device as argument

2020-04-29T02:01:09+00:00

All the imx clocks that need to be registered by the audiomix need to
pass on the device so that the runtime PM support could work properly.

Signed-off-by: Abel Vesa 
Reviewed-by: Stephen Boyd 
Reviewed-by: Peng Fan 
Signed-off-by: Shawn Guo

clk: imx: pll14xx: Add the device as argument when registering

2020-04-29T02:00:42+00:00

In order to allow runtime PM, the device needs to be passed on
to the register function. Audiomix clock controller, used on
i.MX8MP and future platforms, registers a pll14xx and has runtime
PM support.

Signed-off-by: Abel Vesa 
Reviewed-by: Stephen Boyd 
Signed-off-by: Shawn Guo