linux.git/drivers/clk/imx, branch v5.16

clk: imx: use module_platform_driver

2021-12-03T01:57:24+00:00

Replace builtin_platform_driver_probe with module_platform_driver_probe
because CONFIG_CLK_IMX8QXP can be set to =m (kernel module).

Fixes: e0d0d4d86c766 ("clk: imx8qxp: Support building i.MX8QXP clock driver as module")
Cc: Fabio Estevam 
Cc: Stephen Boyd 
Signed-off-by: Miles Chen 
Link: https://lore.kernel.org/r/20210904235418.2442-1-miles.chen@mediatek.com
Reviewed-by: Fabio Estevam 
Reviewed-by: Stephen Boyd 
Signed-off-by: Stephen Boyd

clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites

2021-11-05T22:26:16+00:00

Only imx8m_clk_hw_composite_core needs to set this flag.

Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrappers")
Signed-off-by: Alexander Stein 
Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.com
Reviewed-by: Abel Vesa 
Tested-by: Adam Ford  #imx8mm-beacon
Signed-off-by: Stephen Boyd

clk: imx: Make CLK_IMX8ULP select MXC_CLK

2021-10-06T19:17:42+00:00

Building CLK_IMX8ULP without selecting MXC_CLK causes the following
build errors:

ld: drivers/clk/imx/clk-imx8ulp.o: in function `imx8ulp_clk_cgc2_init':
clk-imx8ulp.c:(.text+0xd0): undefined reference to `imx_ccm_lock'
ld: clk-imx8ulp.c:(.text+0x14f): undefined reference to `imx_clk_hw_pllv4'
ld: clk-imx8ulp.c:(.text+0x15a): undefined reference to `imx_ccm_lock'

Avoid this problem by making CLK_IMX8ULP select MXC_CLK.

Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Reported-by: Randy Dunlap 
Signed-off-by: Fabio Estevam 
Acked-by: Randy Dunlap 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20211006190008.1935051-1-festevam@gmail.com
Signed-off-by: Abel Vesa

clk: imx: imx6ul: Fix csi clk gate register

2021-10-01T07:15:51+00:00

According to the imx6ul Reference Manual the csi clk gate register is
CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
csi clk gate which is the current setting.

Tests have shown though that the correct csi clk gate register for the
imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
register for both platforms.

Signed-off-by: Stefan Riedmueller 
Tested-by: Fabio Estevam 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210927072857.3940880-2-s.riedmueller@phytec.de
Signed-off-by: Abel Vesa

clk: imx: imx6ul: Move csi_sel mux to correct base register

2021-10-01T07:15:51+00:00

The csi_sel mux register is located in the CCM register base and not the
CCM_ANALOG register base. So move it to the correct position in code.

Otherwise changing the parent of the csi clock can lead to a complete
system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely
modified.

Also remove the SET_RATE_PARENT flag since one possible supply for the
csi_sel mux is the system PLL which we don't want to modify.

Signed-off-by: Stefan Riedmueller 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210927072857.3940880-1-s.riedmueller@phytec.de
Signed-off-by: Abel Vesa

clk: imx: Fix the build break when clk-imx8ulp build as module

2021-10-01T07:15:42+00:00

Export the necessary symbols to fix the build break when clk-imx8ulp
build as module

Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Signed-off-by: Jacky Bai 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210917061629.3798360-1-ping.bai@nxp.com
Signed-off-by: Abel Vesa

clk: imx: Add the pcc reset controller support on imx8ulp

2021-09-30T13:22:56+00:00

On i.MX8ULP, for some of the PCCs, it has a peripheral SW RST bit
resides in the same registers as the clock controller. So add this
SW RST controller support alongs with the pcc clock initialization.

the reset and clock shared the same register, to avoid  accessing
the same register by reset control and clock control concurrently,
locking is necessary, so reuse the imx_ccm_lock spinlock to simplify
the code.

Suggested-by: Liu Ying 
Signed-off-by: Jacky Bai 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210914065208.3582128-10-ping.bai@nxp.com
Signed-off-by: Abel Vesa

clk: imx: Add clock driver for imx8ulp

2021-09-30T13:22:56+00:00

Add clock driver for i.MX8ULP.

Signed-off-by: Peng Fan 
Signed-off-by: Jacky Bai 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210914065208.3582128-9-ping.bai@nxp.com
Signed-off-by: Abel Vesa

clk: imx: Update the pfdv2 for 8ulp specific support

2021-09-30T13:22:56+00:00

On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be
set and according to the laest RM, the PFD divider value range
seems will be changed in the future, so update the pfdv2 to
include the specific support for i.MX8ULP.

Signed-off-by: Jacky Bai 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210914065208.3582128-8-ping.bai@nxp.com
Signed-off-by: Abel Vesa

clk: imx: disable the pfd when set pfdv2 clock rate

2021-09-30T13:22:56+00:00

It is possible that a PFD is enabled in HW but not in SW. That
means the enable count & prepare count of the PFD clock is '0',
so the 'CLK_SET_RATE' flag can do nothing when the rate is changed
while the PFD is hw enabled. In order to safely change the pfd
rate, we can disable the PFD directly if it is hw enabled but not
used by SW end user.

Signed-off-by: Jacky Bai 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210914065208.3582128-7-ping.bai@nxp.com
Signed-off-by: Abel Vesa