linux.git/drivers/clk/imx, branch v4.13

clk: imx7d: create clocks behind rawnand clock gate

2017-06-20T02:02:41+00:00

The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.

Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.

Signed-off-by: Stefan Agner 
Tested-by: Fabio Estevam 
Acked-by: Han Xu 
Signed-off-by: Stephen Boyd

clk: imx7d: Fix the DDR PLL enable bit

2017-06-07T00:42:41+00:00

Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.

Fix it accordingly to avoid a kernel hang.

Reported-by: Leonard Crestez 
Signed-off-by: Fabio Estevam 
Reviewed-by: Stefan Agner 
Signed-off-by: Stephen Boyd

clk: imx7d: Fix the powerdown bit location of PLL DDR

2017-06-01T07:25:38+00:00

According to the MX7D Reference Manual the powerdown bit of
CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly.

Signed-off-by: Fabio Estevam 
Reviewed-by: Stefan Agner 
Signed-off-by: Stephen Boyd

clk: imx7d: fix USDHC NAND clock

2017-04-19T16:44:14+00:00

The USDHC NAND root clock is not gated by any CCM clock gate. Remove
the bogus gate definition.

Signed-off-by: Stefan Agner 
Acked-by: Dong Aisheng 
Signed-off-by: Stephen Boyd

clk: imx7d: add the missing ipg_root_clk

2017-04-19T16:10:23+00:00

Add the missing ipg_root_clk which actually is already used by many
orphan clks in current tree.

Cc: Shawn Guo 
Cc: Fabio Estevam 
Reviewed-by: Stefan Agner 
Tested-by: Stefan Agner 
Signed-off-by: Dong Aisheng 
Signed-off-by: Stephen Boyd

clk: clk-imx7d: fix ahb clk definition

2017-04-19T16:10:12+00:00

MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200
used actually is for adc, not ahb. After fix, correct ocram_s_clk
parent accordingly as well.

Cc: Shawn Guo 
Cc: Fabio Estevam 
Reviewed-by: Stefan Agner 
Tested-by: Stefan Agner 
Signed-off-by: Dong Aisheng 
Signed-off-by: Stephen Boyd

clk: imx: correct uart4_serial clock name in driver for i.MX6UL

2017-04-12T16:51:36+00:00

Reviewed-by: Fabio Estevam 
Signed-off-by: Robin van der Gracht 
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock

2017-04-12T16:51:27+00:00

The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register.

Reviewed-by: Fabio Estevam 
Signed-off-by: Robin van der Gracht 
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

Merge branch 'clk-imx7', 'clk-bcm2835' into clk-next

2017-01-26T23:52:37+00:00

* clk-imx7:
  clk: imx7d: Add the OCOTP clock

* clk-bcm2835:
  clk: bcm2835: Add leaf clock measurement support, disabled by default
  clk: bcm2835: Register the DSI0/DSI1 pixel clocks.
  clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.

clk: imx7d: Add the OCOTP clock

2017-01-21T00:27:19+00:00

Add the OCOTP so that this hardware block can be used.

Signed-off-by: Fabio Estevam 
Signed-off-by: Stephen Boyd