linux.git/drivers/clk/imx, branch v4.11

Merge branch 'clk-imx7', 'clk-bcm2835' into clk-next

2017-01-26T23:52:37+00:00

* clk-imx7:
  clk: imx7d: Add the OCOTP clock

* clk-bcm2835:
  clk: bcm2835: Add leaf clock measurement support, disabled by default
  clk: bcm2835: Register the DSI0/DSI1 pixel clocks.
  clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.

clk: imx7d: Add the OCOTP clock

2017-01-21T00:27:19+00:00

Add the OCOTP so that this hardware block can be used.

Signed-off-by: Fabio Estevam 
Signed-off-by: Stephen Boyd

clk: imx6: don't restrict LDB mux changes on QuadPlus

2017-01-20T23:22:37+00:00

The LDB mux/gate layout has been fixed on QuadPlus, so there is no need
to restrict the LDB mux changes on this hardware, as the erratum
preventing this from working properly is gone.

Signed-off-by: Lucas Stach 
Reviewed-by: Fabio Estevam 
Signed-off-by: Stephen Boyd

clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2

2017-01-10T00:06:41+00:00

On vf610, PLL1 and PLL2 have registers to configure fractional part of
frequency multiplier.

This patch adds support for these registers.

This fixes "fast system clock" issue on boards where bootloader sets
fractional multiplier for PLL1.

Suggested-by: Andrey Smirnov 
CC: Chris Healy 
Signed-off-by: Nikita Yushchenko 
Tested-by: Andrey Smirnov 
Signed-off-by: Stephen Boyd

Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2016-12-15T23:15:13+00:00

Pull ARM SoC non-urgent fixes from Arnd Bergmann:
 "As usual, we queue up a few fixes that don't seem urgent enough to go
  in through -rc, or that just came a little too late given their size.

  The zx fixes make the platform finally boot on real hardware, the
  davinci and imx31 get the DT support working better for some of the
  machines that are still normally used with classic board files. One
  tegra fix is important for new bootloader versions, but the bug has
  been around for a while without anyone noticing.

  The other changes are mostly cosmetic"

* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
  arm64: tegra: Add missing Smaug revision
  arm64: tegra: Add VDD_GPU regulator to Jetson TX1
  arm64: dts: zte: clean up gic-v3 redistributor properties
  arm64: dts: zx: Fix gic GICR property
  bus: vexpress-config: fix device reference leak
  soc: ti: qmss: fix the case when !SMP
  ARM: lpc32xx: drop duplicate header device.h
  ARM: ixp4xx: drop duplicate header gpio.h
  ARM: socfpga: fix spelling mistake in error message
  ARM: dts: imx6q-cm-fx6: fix fec pinctrl
  ARM: dts: imx7d-pinfunc: fix UART pinmux defines
  ARM: dts: imx6qp: correct LDB clock inputs
  ARM: OMAP2+: pm-debug: Use seq_putc() in two functions
  ARM: OMAP2+: Remove the omapdss_early_init_of() function
  mfd: tps65217: Fix mismatched interrupt number
  ARM: zx: Fix error handling
  ARM: spear: Fix error handling
  ARM: davinci: da850: Fix pwm name matching
  ARM: clk: imx31: properly init clocks for machines with DT
  clk: imx31: fix rewritten input argument of mx31_clocks_init()
  ...

Merge tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next

2016-11-16T19:16:07+00:00

Pull i.MX clock updates from Shawn Guo:

 - A patch series to fix the long standing issue with glitchy parent
   mux of ldb_di_clk, which can hang up LVDS display when ipu_di_clk
   is sourced from ldb_di_clk.
 - A patch to add imx6ull clock support on top of imx6ul clock driver.

* tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: clk-imx6ul: add clk support for imx6ull
  clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK
  clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only
  clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf

clk: imx: clk-imx6ul: add clk support for imx6ull

2016-11-15T00:55:36+00:00

imx6ull is the derived SoC from imx6ul

Signed-off-by: Peng Fan 
Signed-off-by: Bai Ping 
Signed-off-by: Peter Chen 
Signed-off-by: Shawn Guo

clk: imx: improve precision of AV PLL to 1 Hz

2016-11-02T00:12:50+00:00

The audio and video PLLs are designed to have a precision of 1 Hz if some
conditions are met. The current implementation only allows a precision that
depends on the rate of the parent clock. E.g., if the parent clock is 24
MHz, the precision will be 24 Hz; or more generally the precision will be

    p / 10^6 Hz

where p is the parent clock rate. This comes down to how the register
values for the PLL's fractional loop divider are chosen.

The clock rate calculation for the PLL is

    PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM)

or with a shorter notation

    r = p * (d + a / b)

In addition to all variables being integers, we also have the following
conditions:

    27 <= d <= 54

    -2^29 <= a <= 2^29-1
     0    <  b <= 2^30-1
    |a| < b

Here, d, a and b are register values for the fractional loop divider. We
want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate
function. Currently, d and b are chosen as

    d = r / p
    b = 10^6

hence we get the poor precision. And a is defined in terms of r, d, p and
b:

    a = (r - d * p) * b / p

I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as

    b = p

We can do this since

    |a| < b

    |(r - d * p) * b / p| < b

    |r - d * p| < p

Which have two solutions, one of them is when p < 0, so we can skip that
one. The other is when p > 0 and

    p * (d - 1) < r < p * (d + 1)

Substitute d = r / p:

    (r - p) < r < (r + p)  <=>  p > 0

So, as long as p > 0, we can chose b = p. This is a good choise for b since

    a = (r - d * p) * b / p
      = (r - d * p) * p / p
      = r - d * p

    r = p * (d + a / b)
      = p * d + p * a / b
      = p * d + p * a / p
      = p * d + a

and if d = r / p:

    a = r - d * p
      = r - r / p * p
      = 0

    r = p * d + a
      = p * d + 0
      = p * r / p
      = r

I reckon this is the intention by the design of the clock rate formula.

Signed-off-by: Emil Lundmark 
Reviewed-by: Fabio Estevam 
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd

clk: imx: fix integer overflow in AV PLL round rate

2016-11-02T00:07:54+00:00

Since 'parent_rate * mfn' may overflow 32 bits, the result should be
stored using 64 bits.

The problem was discovered when trying to set the rate of the audio PLL
(pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but
the actual rate returned was 192.000570 MHz. The round rate function should
have been able to return 196.608 MHz, i.e., the desired rate.

Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula")
Cc: Anson Huang 
Signed-off-by: Emil Lundmark 
Reviewed-by: Fabio Estevam 
Acked-by: Shawn Guo 
Signed-off-by: Stephen Boyd

clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK

2016-11-01T12:55:30+00:00

Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk
tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to
enter the ldb_di_ipu_div divider. If the divider gets locked up, no
ldb_di[x]_clk is generated, and the LVDS display will hang when the
ipu_di_clk is sourced from ldb_di_clk.

To fix the problem, both the new and current parent of the ldb_di_clk
should be disabled before the switch. This patch ensures that correct
steps are followed when ldb_di_clk parent is switched in the beginning
of boot. The glitchy muxes are then registered as read-only. The clock
parent can be selected using the assigned-clocks and
assigned-clock-parents properties of the ccm device tree node:

        &clks {
                assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
                                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
                assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>,
                                         <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
        };

The issue is explained in detail in EB821 ("LDB Clock Switch Procedure &
i.MX6 Asynchronous Clock Switching Guidelines") [1].

[1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf

Signed-off-by: Ranjani Vaidyanathan 
Signed-off-by: Fabio Estevam 
Signed-off-by: Philipp Zabel 
Reviewed-by: Akshay Bhat 
Tested-by Joshua Clayton 
Tested-by: Charles Kang 
Signed-off-by: Shawn Guo