linux.git/drivers/clk/bcm, branch v4.9

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2016-11-30T23:15:49+00:00

Pull clk fixes from Stephen Boyd:
 "Two small fixes for MIPI PLLs on sunxi devices and a build fix for a
  Broadcom clk driver having unmet dependencies"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX
  clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
  clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it

clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX

2016-11-23T22:31:11+00:00

With commit f4e871509959 ("clk: iproc: Make clocks visible options"),
COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX
also selects that option, this causes the following Kconfig warning:

warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct
dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) && COMMON_CLK)

Fix this by adding proper depends for COMMON_CLK_IPROC

Fixes: f4e871509959 ("clk: iproc: Make clocks visible options")
Signed-off-by: Florian Fainelli 
Reviewed-by: Ray Jui 
[sboyd@codeaurora.org: Drop default part as it's redundant]
Signed-off-by: Stephen Boyd

clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.

2016-10-17T22:34:36+00:00

Fixes setting low-resolution video modes on HDMI.  Now the PLLH_PIX
divider adjusts itself until the PLLH is within bounds.

Signed-off-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: bcm: Add driver for BCM53573 ILP clock

2016-09-16T23:31:29+00:00

This clock is present on BCM53573 devices (including BCM47189) that use
Cortex-A7. ILP is a part of PMU (Power Management Unit) multi-function
device so we use syscon (and regmap) for it.

Signed-off-by: Rafał Miłecki 
Acked-by: Rob Herring 
[sboyd@codeaurora.org: Remove 0 from clk_init_data to silence sparse]
Signed-off-by: Stephen Boyd

clk: bcm2835: Migrate to clk_hw based registration and OF APIs

2016-09-15T00:35:48+00:00

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Eric Anholt 
Cc: Martin Sperl 
Signed-off-by: Stephen Boyd

clk: iproc: Make clocks visible options

2016-09-15T00:21:47+00:00

Make the clocks visible options that can be selected by anyone.  This
avoids the problems of:
 1) Select is a reverse dependency and is hard for people to understand
    and can sometimes be a pain to track down
 2) Build coverage goes down because configs are hidden
 3) Code bloat

Patch suggested by Stephen Boyd

Signed-off-by: Jon Mason 
Signed-off-by: Stephen Boyd

clk-kona-setup: Use kmalloc_array() in parent_process()

2016-09-14T20:47:33+00:00

A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kmalloc_array".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring 
Reviewed-by: Alex Elder 
[sboyd@codeaurora.org: Save a line]
Signed-off-by: Stephen Boyd

clk: bcm2835: Skip PLLC clocks when deciding on a new clock parent

2016-09-07T15:57:44+00:00

If the firmware had set up a clock to source from PLLC, go along with
it.  But if we're looking for a new parent, we don't want to switch it
to PLLC because the firmware will force PLLC (and thus the AXI bus
clock) to different frequencies during over-temp/under-voltage,
without notification to Linux.

On my system, this moves the Linux-enabled HDMI state machine and DSI1
escape clock over to plld_per from pllc_per.  EMMC still ends up on
pllc_per, because the firmware had set it up to use that.

Signed-off-by: Eric Anholt 
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Acked-by: Martin Sperl 
Signed-off-by: Stephen Boyd

clk: bcm2835: Mark the CM SDRAM clock's parent as critical

2016-09-07T15:57:35+00:00

While the SDRAM is being driven by its dedicated PLL most of the time,
there is a little loop running in the firmware that periodically turns
on the CM SDRAM clock (using its pre-initialized parent) and switches
SDRAM to using the CM clock to do PVT recalibration.

This avoids system hangs if we choose SDRAM's parent for some other
clock, then disable that clock.

Signed-off-by: Eric Anholt 
Acked-by: Martin Sperl 
Signed-off-by: Stephen Boyd

clk: bcm2835: Mark GPIO clocks enabled at boot as critical

2016-09-07T15:57:22+00:00

These divide off of PLLD_PER and are used for the ethernet and wifi
PHYs source PLLs.  Neither of them is currently represented by a phy
device that would grab the clock for us.

This keeps other drivers from killing the networking PHYs when they
disable their own clocks and trigger PLLD_PER's refcount going to 0.

Signed-off-by: Eric Anholt 
Acked-by: Martin Sperl 
Signed-off-by: Stephen Boyd