linux.git/drivers/clk/bcm, branch v4.5

Merge branch 'clk-bcm2835' into clk-next

2015-12-25T04:39:02+00:00

clk: bcm2835: Add PWM clock support

2015-12-25T04:38:38+00:00

Register the pwm clock for bcm2835.

Signed-off-by: Remi Pommarel 
Reviewed-by: Eric Anholt 
Signed-off-by: Michael Turquette

clk: bcm2835: Support for clock parent selection

2015-12-25T04:38:30+00:00

Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
parent clocks. These clocks divide the rate of a parent which can be selected by
setting the proper bits in the clock control register.

Previously all these parents where handled by a mux clock. But a mux clock
cannot be used because updating clock control register to select parent needs a
password to be xor'd with the parent index.

This patch get rid of mux clock and make these clocks handle their own parent,
allowing them to select the one to use.

Signed-off-by: Remi Pommarel 
Reviewed-by: Eric Anholt 
Signed-off-by: Michael Turquette

clk: bcm2835: add a round up ability to the clock divisor

2015-12-25T04:38:06+00:00

Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor
so that the resulting average rate will not be higher than the requested one.

Signed-off-by: Remi Pommarel 
Reviewed-by: Eric Anholt 
Signed-off-by: Michael Turquette

Merge branch 'clk-bcm2835' into clk-next

2015-12-23T00:49:38+00:00

clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.

2015-12-23T00:47:17+00:00

There are a pair of SPI masters and a mini UART that were last minute
additions.  As a result, they didn't get integrated in the same way as
the other gates off of the VPU clock in CPRMAN.

Signed-off-by: Eric Anholt 
Signed-off-by: Michael Turquette

clk: bcm: Add BCM63138 clock support

2015-11-20T23:46:27+00:00

BCM63138 has a simple clocking domain which is primarily the ARMPLL
clocking complex, from which the ARM (CPU), APB and AXI clocks would be
derived from.

Since the ARMPLL controller is entirely compatible with the iProc ARM
PLL, we just initialize it without additional parameters.

Signed-off-by: Florian Fainelli 
Signed-off-by: Stephen Boyd

Merge branch 'clk-iproc' into clk-next

2015-10-22T00:28:19+00:00

* clk-iproc:
  clk: iproc: define Broadcom NS2 iProc clock binding
  clk: iproc: define Broadcom NSP iProc clock binding
  clk: ns2: add clock support for Broadcom Northstar 2 SoC
  clk: iproc: Separate status and control variables
  clk: iproc: Split off dig_filter
  clk: iproc: Add PLL base write function
  clk: nsp: add clock support for Broadcom Northstar Plus SoC
  clk: iproc: Add PWRCTRL support
  clk: cygnus: Convert all macros to all caps
  ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled

clk: ns2: add clock support for Broadcom Northstar 2 SoC

2015-10-22T00:22:58+00:00

The Broadcom Northstar 2 SoC is architected under the iProc
architecture. It has the following PLLs: GENPLL SCR, GENPLL SW,
LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.

Signed-off-by: Jon Mason 
Signed-off-by: Stephen Boyd

clk: iproc: Separate status and control variables

2015-10-22T00:03:41+00:00

Some PLLs have separate registers for Status and Control.  The means the
pll_base needs to be split into 2 new variables, so that those PLLs can
specify device tree registers for those independently.  Also, add a new
driver flag to identify this presence of the split, and let the driver
know that additional registers need to be used.

Signed-off-by: Jon Mason 
Signed-off-by: Stephen Boyd