linux.git/drivers/clk/bcm, branch v4.13

clk: iproc: Remove __init marking on iproc_pll_clk_setup()

2017-06-21T16:12:57+00:00

Now that this function is called from driver probe routines, it
needs to drop the __init marking because it isn't just called
from init code.

Reported-by: Stephen Rothwell 
Cc: Sandeep Tripathy 
Cc: Anup Patel 
Cc: Ray Jui 
Cc: Scott Branden 
Fixes: 654cdd3229cd ("clk: bcm: Add clocks for Stingray SOC")
Signed-off-by: Stephen Boyd

clk: bcm: Add clocks for Stingray SOC

2017-06-20T02:02:45+00:00

This patch adds support for Stingray clocks in iproc
ccf. The Stingray SOC has various plls based on iproc
pll architecture.

Signed-off-by: Sandeep Tripathy 
Signed-off-by: Anup Patel 
Reviewed-by: Ray Jui 
Reviewed-by: Scott Branden 
Signed-off-by: Stephen Boyd

clk: bcm2835: Minimise clock jitter for PCM clock

2017-06-02T22:42:21+00:00

Fractional clock dividers generate accurate average frequencies but
with jitter, particularly when the integer divisor is small.

Introduce a new metric of clock accuracy to penalise clocks with a good
average but worse jitter compared to clocks with an average which is no
better but with lower jitter. The metric is the ideal rate minus the
worse deviation from that ideal using the nearest integer divisors.

Use this metric for parent selection for clocks requiring low jitter
(currently just PCM).

Signed-off-by: Phil Elwell 
Reviewed-by: Eric Anholt 
Acked-by: Stefan Wahren 
Signed-off-by: Stephen Boyd

clk: bcm2835: Limit PCM clock to OSC and PLLD_PER

2017-06-02T22:42:19+00:00

Restrict clock sources for the PCM peripheral to the oscillator and
PLLD_PER because other source may have varying rates or be switched off.
Prevent other sources from being selected by replacing their names in
the list of potential parents with dummy entries (entry index is
significant).

Signed-off-by: Phil Elwell 
Reviewed-by: Eric Anholt 
Acked-by: Stefan Wahren 
Signed-off-by: Stephen Boyd

clk: bcm2835: Correct the prediv logic

2017-06-02T22:41:49+00:00

If a clock has the prediv flag set, both the integer and fractional
parts must be scaled when calculating the resulting frequency.

Signed-off-by: Phil Elwell 
Signed-off-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: ns2: Correct SDIO bits

2017-04-19T16:50:39+00:00

Corrected the bits for power and iso.

Signed-off-by: Bharat Kumar Reddy Gooty 
Signed-off-by: Jon Mason 
Fixes: f7225a83 ("clk: ns2: add clock support for Broadcom Northstar 2 SoC")
Signed-off-by: Stephen Boyd

clk: iproc: Remove redundant check

2017-04-12T16:50:54+00:00

Remove the redundant check of 'rate' in the if statement of the
'pll_set_rate' function

Reported-by: David Binderman 
Signed-off-by: Ray Jui 
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: bcm2835: Add leaf clock measurement support, disabled by default

2017-01-21T00:22:56+00:00

This proved incredibly useful during debugging of the DSI driver, to
see if our clocks were running at rate we requested.  Let's leave it
here for the next person interacting with clocks on the platform (and
so that hopefully we can just hook it up to debugfs some day).

Signed-off-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: bcm2835: Register the DSI0/DSI1 pixel clocks.

2017-01-21T00:22:55+00:00

The DSI pixel clocks are muxed from clocks generated in the analog phy
by the DSI driver.  In order to set them as parents, we need to do the
same name lookup dance on them as we do for our root oscillator.

Signed-off-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.

2017-01-21T00:22:54+00:00

Our core PLLs are intended to be configured once and left alone.  With
the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
change PLLD just to get closer to the requested DSI clock, thus
changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
it, and breaking ethernet.

We *do* want PLLH to change so that PLLH_AUX can be exactly the value
we want, though.  Thus, we need to have a per-divider policy of
whether to pass rate changes up.

Signed-off-by: Eric Anholt 
Signed-off-by: Stephen Boyd