linux.git/drivers/clk/at91, branch v5.9

clk: at91: sama7g5: add clock support for sama7g5

2020-07-24T09:19:09+00:00

Add clock support for SAMA7G5.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-19-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-utmi: add utmi support for sama7g5

2020-07-24T09:19:08+00:00

Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-18-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs

2020-07-24T09:19:08+00:00

Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
For these, split the PLL clock in two: fractional clock and
divider clock. In case PLLs supports multiple outputs (since these
outputs are dividers (with different settings) sharing the same
fractional part), it will register one fractional clock and multiple
divider clocks (dividers sharing the fractional clock).

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-17-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-programmable: add mux_table option

2020-07-24T09:19:08+00:00

Add mux table option. This is necessary for IP versions that has
gaps in the range of available clock sources (e.g. SAMA7G5).

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-15-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-peripheral: add support for changeable parent rate

2020-07-24T09:19:08+00:00

Some peripheral clocks on SAMA7G5 supports requesting parent to change
its rate (image related clocks: csi, csi2dc, isc). Add support
so that if registered with this option the clock rate to be
requested from parent.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-14-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-master: add master clock support for SAMA7G5

2020-07-24T09:19:08+00:00

Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-generated: add mux_table option

2020-07-24T09:19:08+00:00

Add mux table option. This is necessary for IP versions that has
gaps in the range of available clock sources (e.g. SAMA7G5).

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-generated: pass the id of changeable parent at registration

2020-07-24T09:19:08+00:00

Pass the ID of changeable parent at registration. This will allow
the scalability of this clock driver with regards to the changeable
parent ID for versions of this IP where changeable parent is not the
last one in the parents list (e.g. SAMA7G5). With this the clock flags
are set to zero in case we have no changeable parent. Also in
clk_generated_best_diff() the *best_diff variable is check against
tmp_diff variable using ">=" operator instead of ">" so that in case
the requested frequency could be obtained using fix parents + gck
dividers but the clock also supports changeable parent to be able
to force the usage of the changeable parent.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: replace conditional operator with double logical not

2020-07-24T09:19:08+00:00

Replace conditional operator with double logical not as code
may be simpler to read.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: sckc: register slow_rc with accuracy option

2020-07-24T09:19:08+00:00

Chapter 57.7.5 of SAM9X60 datasheet specifies that the maximum drift of
this oscillator is +- 3KHz. Use that value and the formula at [1]
or the calculator at [2] to compute the PPB value.

[1] https://www.everythingrf.com/rf-calculators/ppm-to-hz-calculator
[2] https://www.changpuak.ch/electronics/ppm_to_Hz_converter.php

Fixes: 04bcc4275e601 ("clk: at91: sckc: add support for SAM9X60")
Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1595403506-8209-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd