linux.git/drivers/clk/at91, branch v5.13

clk: at91: Trivial typo fixes in the file sama7g5.c

2021-03-13T21:02:02+00:00

s/critial/critical/  ......two different places
s/parrent/parent/

Signed-off-by: Bhaskar Chowdhury 
Link: https://lore.kernel.org/r/20210313053222.14706-1-unixbhaskar@gmail.com
Acked-by: Randy Dunlap 
Signed-off-by: Stephen Boyd

clk: at91: Fix the declaration of the clocks

2021-02-10T00:54:44+00:00

These are all "early clocks" that require initialization just at
of_clk_init() time. Use CLK_OF_DECLARE() to declare them.

This also fixes a problem that was spotted when fw_devlink was
set to 'on' by default: the boards failed to boot. The reason is
that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes
the consumers of the clock to be postponed by fw_devlink until
the second initialization routine of the clock has been completed.
One of the consumers of the clock is the timer, which is used as a
clocksource, and needs the clock initialized early. Postponing the
timers caused the fail at boot.

Signed-off-by: Tudor Ambarus 
Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com
Acked-by: Saravana Kannan 
Tested-by: Eugen Hristev 
Acked-by: Nicolas Ferre 
Reviewed-by: Claudiu Beznea 
Signed-off-by: Stephen Boyd

clk: at91: sam9x60: remove atmel,osc-bypass support

2020-12-19T23:33:00+00:00

The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
bypass.

Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Reported-by: Claudiu Beznea 
Signed-off-by: Alexandre Belloni 
Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.com
Reviewed-by: Claudiu Beznea 
Tested-by: Claudiu Beznea 
Signed-off-by: Stephen Boyd

clk: at91: sama7g5: register cpu clock

2020-12-19T19:50:56+00:00

Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-master: re-factor master clock

2020-12-19T19:50:56+00:00

Re-factor master clock driver by splitting it into 2 clocks: prescaller
and divider clocks. Based on registered clock flags the prescaler's rate
could be changed at runtime. This is necessary for platforms supporting
DVFS (e.g. SAMA7G5) where master clock could be changed at run-time.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz

2020-12-19T19:50:56+00:00

Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: sama7g5: decrease lower limit for MCK0 rate

2020-12-19T19:50:56+00:00

On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
The lower limit is changed to be able to set MCK0 accordingly by
DVFS.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: sama7g5: remove mck0 from parent list of other clocks

2020-12-19T19:50:56+00:00

MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
are glitch free aware at MCK0 changes, remove MCK0 from parent list
of other clocks (e.g. generic clock, programmable/system clock, MCKX).

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: clk-sam9x60-pll: allow runtime changes for pll

2020-12-19T19:50:55+00:00

Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.

Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd

clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics

2020-12-19T19:50:55+00:00

This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain 
Signed-off-by: Eugen Hristev 
Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd