Pull clock framework changes from Mike Turquette:
 "The clock framework changes for 3.15 look similar to past pull
  requests.  Mostly clock driver updates, more Device Tree support in
  the form of common functions useful across platforms and a handful of
  features and fixes to the framework core"

* tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: shmobile: fix setting paretn clock rate
  clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
  clk: Fix minor errors in of_clk_init() function comments
  clk: reverse default clk provider initialization order in of_clk_init()
  clk: sirf: update copyright years to 2014
  clk: mmp: try to use closer one when do round rate
  clk: mmp: fix the wrong calculation formula
  clk: mmp: fix wrong mask when calculate denominator
  clk: st: Adds quadfs clock binding
  clk: st: Adds clockgen-vcc and clockgen-mux clock binding
  clk: st: Adds clockgen clock binding
  clk: st: Adds divmux and prediv clock binding
  clk: st: Support for A9 MUX clocks
  clk: st: Support for ClockGenA9/DDR/GPU
  clk: st: Support for QUADFS inside ClockGenB/C/D/E/F
  clk: st: Support for VCC-mux and MUX clocks
  clk: st: Support for PLLs inside ClockGenA(s)
  clk: st: Support for DIVMUX and PreDiv Clocks
  clk: support hardware-specific debugfs entries
  clk: s2mps11: Use of_get_child_by_name
  ...

The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s)

DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s)
It includes support for each channel : 3-parent Multiplexer,
Divider for each Parent, Gate to switch OFF the output channel. The
clock is implemented using generic clocks implemented in the kernel
clk_divider and clk_mux.

PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide
the oscillator clock by factor-of-16. The clock is implemented using
generic clocks implemented in the kernel clk_divider.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

updating clock drivers for Hisilicon

Now only fixed rate clocks are appended into the clock driver.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

MOXA ART SoCs allow to determine PLL output and APB frequencies
by reading registers holding multiplier and divisor information.

Add a clock driver for this SoC.

Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

Add code for device tree support of clocks in the BCM281xx family of
SoCs.  Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs).  (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)

A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC.  A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers.  There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more).  There are also "fractional" dividers which allow
division by non-integer values.  To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.

If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed.  The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.

The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock.  Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate.  (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)

The source code is divided into three general portions:

    drivers/clk/bcm/clk-kona.h
    drivers/clk/bcm/clk-kona.c
        These implement the basic Kona clock functionality,
        including the clk_ops methods and various routines to
        manipulate registers and interpret their values.  This
        includes some functions used to set clocks to a desired
        initial state (though this feature is only partially
        implemented here).

    drivers/clk/bcm/clk-kona-setup.c
        This contains generic run-time initialization code for
        data structures representing Kona CCUs and clocks.  This
        encapsulates the clock structure initialization that can't
        be done statically.  Note that there is a great deal of
        validity-checking code here, making explicit certain
        assumptions in the code.   This is mostly useful for adding
        new clock definitions and could possibly be disabled for
        production use.

    drivers/clk/bcm/clk-bcm281xx.c
        This file defines the specific CCUs used by BCM281XX family
        SoCs, as well as the specific clocks implemented by each.
        It declares a device tree clock match entry for each CCU
        defined.

    include/dt-bindings/clock/bcm281xx.h
        This file defines the selector (index) values used to
        identify a particular clock provided by a CCU.  It consists
        entirely of C preprocessor constants, to be used by both the
        C source and device tree source files.

Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>

Pull more clock framework changes from Mike Turquette:
 "The second half of the clock framework pull requeust for 3.14 is
  dominated by platform support for Qualcomm's MSM SoCs, DT binding
  updates for TI's OMAP-ish processors and additional support for
  Samsung chips.

  Additionally there are other smaller clock driver changes and several
  last minute fixes.  This pull request also includes the HiSilicon
  support that depends on the already-merged arm-soc pull request"

[ Fix up stupid compile error in the source tree with evil merge  - Grumpy Linus ]

* tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux: (49 commits)
  clk: sort Makefile
  clk: sunxi: fix overflow when setting up divided factors
  clk: Export more clk-provider functions
  dt-bindings: qcom: Fix warning with duplicate dt define
  clk: si5351: remove variant from platform_data
  clk: samsung: Remove unneeded semicolon
  clk: qcom: Fix modular build
  ARM: OMAP3: use DT clock init if DT data is available
  ARM: AM33xx: remove old clock data and link in new clock init code
  ARM: AM43xx: Enable clock init
  ARM: OMAP: DRA7: Enable clock init
  ARM: OMAP4: remove old clock data and link in new clock init code
  ARM: OMAP2+: io: use new clock init API
  ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
  ARM: OMAP3: hwmod: initialize clkdm from clkdm_name
  ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm
  ARM: OMAP2+: clock: use driver API instead of direct memory read/write
  ARM: OMAP2+: clock: add support for indexed memmaps
  ARM: dts: am43xx clock data
  ARM: dts: AM35xx: use DT clock data
  ...

Signed-off-by: Mike Turquette <mturquette@linaro.org>

Pull clk framework changes from Mike Turquette:
 "The first half of the clk framework pull request is made up almost
  entirely of new platform/driver support.  There are some conversions
  of existing drivers to the common-clock Device Tree binding, and a few
  non-critical fixes to the framework.

  Due to an entirely unnecessary cyclical dependency with the arm-soc
  tree this pull request is broken into two pieces.  The second piece
  will be sent out after arm-soc sends you the pull request that merged
  in core support for the HiSilicon 3620 platform.  That same pull
  request from arm-soc depends on this pull request to merge in those
  HiSilicon bits without causing build failures"

[ Just did the ARM SoC merges, so getting ready for the second clk tree
  pull request   - Linus ]

* tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits)
  devicetree: bindings: Document qcom,mmcc
  devicetree: bindings: Document qcom,gcc
  clk: qcom: Add support for MSM8660's global clock controller (GCC)
  clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8974's global clock controller (GCC)
  clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)
  clk: qcom: Add support for MSM8960's global clock controller (GCC)
  clk: qcom: Add reset controller support
  clk: qcom: Add support for branches/gate clocks
  clk: qcom: Add support for root clock generators (RCGs)
  clk: qcom: Add support for phase locked loops (PLLs)
  clk: qcom: Add a regmap type clock struct
  clk: Add set_rate_and_parent() op
  reset: Silence warning in reset-controller.h
  clk: sirf: re-arch to make the codes support both prima2 and atlas6
  clk: composite: pass mux_hw into determine_rate
  clk: shmobile: Fix MSTP clock array initialization
  clk: shmobile: Fix MSTP clock index
  ARM: dts: Add clock provider specific properties to max77686 node
  clk: max77686: Register OF clock provider
  ...

Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific clock names.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>