linux.git/drivers/clk/Makefile, branch master

Merge branches 'clk-pile' and 'clk-microchip' into clk-next

2026-08-20T23:51:47+00:00

* clk-pile: (111 commits)
  clk: microchip: mpfs: fix regmap_update_bits() mask/val order
  clk: visconti: Make sure clk_init_data is fully initialized
  clk: ti: Make sure clk_init_data is fully initialized
  MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem
  Drop Michael Turquette's clk maintainer entry
  clk: ti: composite: resolve parent clocks by DT index, not by name
  clk: ti: mux: resolve parent clocks by DT index, not by name
  clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
  dt-bindings: clock: ti,keystone-gate: Convert to DT schema
  dt-bindings: clock: ti: Convert APLL clock to DT schema
  clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
  dt-bindings: clock: ti,clockdomain: Convert to DT schema
  dt-bindings: clock: Correct white-space style
  clk: tegra: set up proper EMC clock implementation for Tegra114
  clk: clocking-wizard: remove 20kHz restriction
  clk: clocking-wizard: optimize clock search
  clk: clocking-wizard: fix clock difference detection
  clk: mediatek: mt8135: Fix inverted gate control for devapc_ck
  clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig
  clk: tegra: support 48MHz clock for pll_p_out1
  ...

* clk-microchip:
  clk: at91: Read "reg" with helper

Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

2026-08-17T16:28:08+00:00

Pull clk patches from Brian Masney:

 - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS),
   UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree
   bindings. Si549 support was added to the existing si544 driver.
 - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha
   EN7523 PCIe PERSTOUT reset lines.
 - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to
   the existing optional variant, and exports
   devm_clk_hw_register_composite_pdata() for modular drivers.
 - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1
   support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL
   charge pump/lock parameter programming during dynamic reconfiguration.
 - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in
   the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted
   gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on
   registration failure, a prepare reference leak in the palmas driver,
   unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in
   pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a
   clocking-wizard clock difference detection bug.
 - Various cleanups across tegra, st, and mvebu providers to stop misusing the
   consumer clock API, along with other minor fixes and improvements.

Signed-off-by: Brian Masney 

* tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits)
  clk: tegra: set up proper EMC clock implementation for Tegra114
  clk: clocking-wizard: remove 20kHz restriction
  clk: clocking-wizard: optimize clock search
  clk: clocking-wizard: fix clock difference detection
  clk: mediatek: mt8135: Fix inverted gate control for devapc_ck
  clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig
  clk: tegra: support 48MHz clock for pll_p_out1
  clk: aspeed: add AST2700 PECI clock
  dt-bindings: clock: ast2700: add PECI clock
  clk: mediatek: Add mt8173-mfgtop driver
  dt-bindings: clock: mediatek: Add mt8173 mfgtop
  clk: tegra: clean-up simple provider misuse of the consumer API
  clk: st: clean-up simple provider misuse of the consumer API
  clk: mvebu: clean-up simple provider misuse of the consumer API
  clk: remove conditional return with no effect
  clk: Add devm_clk_bulk_get_enable()
  clk: en7523: add support for dedicated PCIe PERSTOUT reset
  dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT
  arm64: dts: cix: sky1: add audss cru
  reset: cix: add sky1 audss auxiliary reset driver
  ...

Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

2026-08-17T16:27:10+00:00

Pull clk patches picked up by Brian Masney:

Here's various improvements and fixes for the clk subsystem that was posted prior
to the opening of the last merge window.

- Add spread spectrum clock (SSC) support to the clk framework, including a new
  assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum()
  API with KUnit tests (Peng Fan)
- Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a
  common SCMI clock header (Peng Fan)
- Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and
  reset generator (Xuyang Dong)
- Add clk_determine_rate_noop() helper for clock drivers that can do any rate,
  and convert existing open-coded implementations across hisilicon, imx, qcom,
  renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain
  drivers (Brian Masney)
- Add kernel-doc documentation for struct clk_core and the core clock flags,
  and wire up clk identifiers into the documentation build (Brian Masney)
- Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum
  rate for large rate requests, with KUnit tests (Lad Prabhakar)
- Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64
  return values, incorrect PLL_CTL1_FRAC bit field width, and broken
  determine_rate logic (Joey Lu)
- Support unique clock names for multi-socket Tegra platforms (Jon Hunter)
- Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev)
- Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov,
  Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak,
  Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König,
  William Theesfeld, Xuyang Dong, and Yu-Chun Lin

Signed-off-by: Brian Masney 
[sboyd@kernel.org: Fix allmodconfig modpost failure in scmi]

* tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits)
  pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop()
  pmdomain: mediatek: airoha: use clk_determine_rate_noop()
  phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop()
  clk: sprd: use clk_determine_rate_noop()
  clk: scpi: use clk_determine_rate_noop()
  clk: samsung: acpm: use clk_determine_rate_noop()
  clk: rp1: use clk_determine_rate_noop()
  clk: renesas: rzg2l-cpg: use clk_determine_rate_noop()
  clk: qcom: smd-rpm: use clk_determine_rate_noop()
  clk: qcom: rpmh: use clk_determine_rate_noop()
  clk: qcom: rpm: use clk_determine_rate_noop()
  clk: imx: scu: use clk_determine_rate_noop()
  clk: hisilicon: hi3660-stub: use clk_determine_rate_noop()
  clk: add clk_determine_rate_noop()
  clk: imx: scu: drop redundant init.ops variable assignment
  clk: test: convert constants to use HZ_PER_MHZ
  docs: clk: include some identifiers to keep documentation up to date
  clk: add kernel docs for struct clk_core
  clk: add kernel docs for the core flags
  clk: hisilicon: allow COMPILE_TEST builds
  ...

clk: cix: add sky1 audss clock controller

2026-07-28T15:25:29+00:00

Add a platform driver for the Cix Sky1 AUDSS CRU. The driver maps
the CRU registers and registers mux, divider and gate clocks for
DSP, SRAM, HDA, DMAC, I2S, mailbox, watchdog and timer blocks.

Four SoC-level audio reference clocks are enabled as inputs to the
internal clock tree. The driver releases the AUDSS NOC reset, enables
runtime PM and instantiates the auxiliary reset device.

Signed-off-by: Joakim Zhang 
Reviewed-by: Brian Masney 
Signed-off-by: Brian Masney

clk: ultrarisc: Add DP1000 clock driver

2026-07-28T15:25:29+00:00

Add a clock driver for the UltraRISC DP1000 SoC.

The clock tree is driven by a SYSPLL and provides fixed-factor clocks for
the subsystem and PCIe, divider-based root clocks for GMAC and the UART,
I2C, and SPI blocks, and per-instance gate clocks for UART0-3, I2C0-3,
and SPI0-1.

Signed-off-by: Jia Wang 
Reviewed-by: Brian Masney 
Signed-off-by: Brian Masney

clk: stm32: allow STM32MP COMPILE_TEST builds

2026-07-28T15:25:29+00:00

COMMON_CLK_STM32MP already allows COMPILE_TEST, but the parent clock
Makefile only descends into drivers/clk/stm32 for ARCH_STM32.  Use the
STM32MP clock symbol for that directory gate instead.

Tested with:
make LLVM=1 ARCH=loongarch drivers/clk/stm32/

Assisted-by: Codex:GPT-5.5
Signed-off-by: Rosen Penev 
Reviewed-by: Brian Masney 
Signed-off-by: Brian Masney

clk: thead: allow COMPILE_TEST builds

2026-07-15T04:42:01+00:00

Follow the pattern of many other directories in this Makefile (sunxi-ng,
tenstorrent, ti, etc.) by using obj-y. This allows COMPILE_TEST to
select the driver without having CONFIG_ARCH_THEAD enabled

Tested with:
make LLVM=1 ARCH=loongarch drivers/clk/thead/

Assisted-by: Codex:GPT-5.5
Acked-by: Drew Fustini 
Reviewed-by: Brian Masney 
Signed-off-by: Rosen Penev 
Signed-off-by: Drew Fustini

clk: hisilicon: allow COMPILE_TEST builds

2026-06-29T20:50:18+00:00

The HiSilicon clock symbols already depend on ARCH_HISI or COMPILE_TEST,
but the parent clock Makefile only descends into the hisilicon directory
when ARCH_HISI is enabled.

Add a hidden family gate selected by the HiSilicon clock and reset symbols,
default it for ARCH_HISI, and use it for the parent Makefile descent.  This
keeps existing platform builds unchanged while allowing compile-test
coverage.

Tested with:
make LLVM=1 ARCH=loongarch drivers/clk/hisilicon/

Assisted-by: Codex:GPT-5.5
Signed-off-by: Rosen Penev 
Reviewed-by: Brian Masney 
Signed-off-by: Brian Masney

clk: divider: Add KUnit tests for clk_divider_bestdiv() ULONG_MAX handling

2026-06-29T17:18:50+00:00

Add KUnit tests to verify the behaviour of clk_divider_bestdiv() when
clk_round_rate() is called with ULONG_MAX, which is the canonical way
to probe the maximum rate a clock can produce.

Two test cases are introduced:

- clk_divider_bestdiv_ulong_max_returns_max_rate: registers a 1 GHz
  fixed-rate parent driving a table-based divider whose smallest entry
  is div=2 (entries: 2, 4, 8). Calls clk_hw_round_rate(div_hw, ULONG_MAX)
  and checks the result.

- clk_divider_bestdiv_mux_ulong_max_returns_max_rate: places a two-input
  mux (4 GHz and 2 GHz fixed-rate parents, CLK_SET_RATE_PARENT) ahead of
  the same table-based divider to verify correct parent selection under
  ULONG_MAX.

Both tests use an explicit clk_div_table with a minimum divider of 2 so
that the pre-loop maxdiv clamping in clk_divider_bestdiv():

    maxdiv = min(ULONG_MAX / rate, maxdiv);

clamps maxdiv to 1, causing _next_div() to return 2 on the first
iteration and skip the loop body entirely. This makes bestdiv fall back
to the maximum divider, returning the minimum rate rather than the
maximum.

The expected values intentionally reflect the buggy output:
  - test 1: PARENT_RATE_1GHZ / 8  (minimum rate, not maximum)
  - test 2: 0                      (invalid, loop never populated bestdiv)

These will be corrected to PARENT_RATE_1GHZ / 2 and PARENT_RATE_4GHZ / 2
respectively once the fix to clk_divider_bestdiv() is applied.

Signed-off-by: Lad Prabhakar 
Reviewed-by: Brian Masney 
Signed-off-by: Brian Masney

clk: scmi: Add i.MX95 OEM extension support for SCMI clock driver

2026-06-29T17:16:17+00:00

 - Introduce 'clk-scmi-oem.c' to support vendor-specific OEM extensions
   for the SCMI clock driver, allows clean integration of vendor-specific
   features without impacting the core SCMI clock driver logic.
 - Extend 'clk-scmi.h' with 'scmi_clk_oem' structure and related
   declarations.
 - Initialize OEM extensions via 'scmi_clk_oem_init()'.
 - Support querying OEM-specific features and setting spread spectrum.
 - Pass 'scmi_device' to 'scmi_clk_ops_select()' for OEM data access.

Reviewed-by: Sebin Francis 
Reviewed-by: Cristian Marussi 
Signed-off-by: Peng Fan 
Signed-off-by: Brian Masney