linux.git/drivers/clk/Kconfig, branch v5.16 Linux kernel source tree clk: pistachio: Make it selectable for generic MIPS kernel 2021-08-12T14:01:49+00:00 Jiaxun Yang jiaxun.yang@flygoat.com 2021-07-23T02:25:37+00:00 90429205c000f4befdc212cfade39e358292584c We're moving pistachio to generic MIPS kernel. The clk driver should be avilable to the generic MIPS kernel. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
We're moving pistachio to generic MIPS kernel. The clk driver
should be avilable to the generic MIPS kernel.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-ingenic' into clk-next 2021-06-29T20:33:22+00:00 Stephen Boyd sboyd@kernel.org 2021-06-29T20:33:22+00:00 4f47c91fc6a8f4b274d934648b53cb668c69c986 - Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs - Support secure mode of STM32MP1 SoCs - Improve clock support for Actions S500 SoC * clk-lmk04832: clk: lmk04832: Use of match table clk: lmk04832: Depend on SPI clk: lmk04832: add support for digital delay clk: add support for the lmk04832 dt-bindings: clock: add ti,lmk04832 bindings * clk-stm: clk: stm32mp1: new compatible for secure RCC support dt-bindings: clock: stm32mp1 new compatible for secure rcc dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 reset: stm32mp1: remove stm32mp1 reset clk: stm32mp1: move RCC reset controller into RCC clock driver clk: stm32mp1: convert to module driver clk: stm32mp1: remove intermediate pll clocks clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock * clk-rohm: clk: bd718xx: Drop BD70528 support * clk-actions: clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC clk: actions: Fix SD clocks factor table on Owl S500 SoC clk: actions: Fix UART clock dividers on Owl S500 SoC * clk-ingenic: clk: ingenic: Add support for the JZ4760 clk: ingenic: Support overriding PLLs M/N/OD calc algorithm clk: ingenic: Remove pll_info.no_bypass_bit clk: ingenic: Read bypass register only when there is one clk: Support bypassing dividers dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles 
 - Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock
   Jitter Cleaner With Dual Loop PLLs
 - Support secure mode of STM32MP1 SoCs
 - Improve clock support for Actions S500 SoC

* clk-lmk04832:
  clk: lmk04832: Use of match table
  clk: lmk04832: Depend on SPI
  clk: lmk04832: add support for digital delay
  clk: add support for the lmk04832
  dt-bindings: clock: add ti,lmk04832 bindings

* clk-stm:
  clk: stm32mp1: new compatible for secure RCC support
  dt-bindings: clock: stm32mp1 new compatible for secure rcc
  dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15
  dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
  dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
  reset: stm32mp1: remove stm32mp1 reset
  clk: stm32mp1: move RCC reset controller into RCC clock driver
  clk: stm32mp1: convert to module driver
  clk: stm32mp1: remove intermediate pll clocks
  clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
  clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clock

* clk-rohm:
  clk: bd718xx: Drop BD70528 support

* clk-actions:
  clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC
  dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC
  clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC
  clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC
  clk: actions: Fix SD clocks factor table on Owl S500 SoC
  clk: actions: Fix UART clock dividers on Owl S500 SoC

* clk-ingenic:
  clk: ingenic: Add support for the JZ4760
  clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
  clk: ingenic: Remove pll_info.no_bypass_bit
  clk: ingenic: Read bypass register only when there is one
  clk: Support bypassing dividers
  dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatibles
clk: lmk04832: Depend on SPI 2021-06-29T06:08:50+00:00 Stephen Boyd sboyd@kernel.org 2021-06-29T06:07:50+00:00 97a1c5cbbfe4b84573df2edc6b782132f8e012ad This driver depends on SPI. Otherwise compilation fails clk-lmk04832.c:(.text+0x1668): undefined reference to `spi_get_device_id' Reported-by: kernel test robot <lkp@intel.com> Cc: Liam Beguin <lvb@xiphos.com> Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Link: https://lore.kernel.org/r/20210629060751.3119453-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
This driver depends on SPI. Otherwise compilation fails

  clk-lmk04832.c:(.text+0x1668): undefined reference to `spi_get_device_id'

Reported-by: kernel test robot <lkp@intel.com>
Cc: Liam Beguin <lvb@xiphos.com>
Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832")
Link: https://lore.kernel.org/r/20210629060751.3119453-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: stm32mp1: new compatible for secure RCC support 2021-06-28T23:09:10+00:00 Gabriel Fernandez gabriel.fernandez@foss.st.com 2021-06-17T05:18:14+00:00 21e743300dd0b9e57425de4a9ba651493b165e03 Platform STM32MP1 can be used in configuration where some clock resources cannot be accessed by Linux kernel when executing in non-secure state of the CPU(s). In such configuration, the RCC clock driver must not register clocks it cannot access. They are expected to be registered from another clock driver such as the SCMI clock driver. This change uses specific compatible string "st,stm32mp1-rcc-secure" to specify RCC clock driver configuration where RCC is secure. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-12-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Platform STM32MP1 can be used in configuration where some clock
resources cannot be accessed by Linux kernel when executing in non-secure
state of the CPU(s).
In such configuration, the RCC clock driver must not register clocks
it cannot access.
They are expected to be registered from another clock driver such
as the SCMI clock driver.
This change uses specific compatible string "st,stm32mp1-rcc-secure"
to specify RCC clock driver configuration where RCC is secure.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20210617051814.12018-12-gabriel.fernandez@foss.st.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: bd718xx: Drop BD70528 support 2021-06-28T01:42:45+00:00 Matti Vaittinen matti.vaittinen@fi.rohmeurope.com 2021-05-25T10:15:10+00:00 fa5b6541423e7e1fb5deeacc36abea9163d23720 The only known BD70528 use-cases are such that the PMIC is controlled from separate MCU which is not running Linux. I am not aware of any Linux driver users. Furthermore, it seems there is no demand for this IC. Let's ease the maintenance burden and drop the driver. We can always add it back if there is sudden need for it. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Link: https://lore.kernel.org/r/937ed0828486a08e2d00bce2815d491c1c9c49b4.1621937490.git.matti.vaittinen@fi.rohmeurope.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
The only known BD70528 use-cases are such that the PMIC is controlled
from separate MCU which is not running Linux. I am not aware of
any Linux driver users. Furthermore, it seems there is no demand for
this IC. Let's ease the maintenance burden and drop the driver. We can
always add it back if there is sudden need for it.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Link: https://lore.kernel.org/r/937ed0828486a08e2d00bce2815d491c1c9c49b4.1621937490.git.matti.vaittinen@fi.rohmeurope.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: add support for the lmk04832 2021-06-28T01:02:50+00:00 Liam Beguin lvb@xiphos.com 2021-04-23T00:40:55+00:00 3bc61cfd6f4a57de32132075b15b0ac8987ced1d The LMK04832 is an ultra-high performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20210423004057.283926-2-liambeguin@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
The LMK04832 is an ultra-high performance clock conditioner with JEDEC
JESD204B support and is also pin compatible with the LMK0482x family of
devices.

Signed-off-by: Liam Beguin <lvb@xiphos.com>
Link: https://lore.kernel.org/r/20210423004057.283926-2-liambeguin@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clkdev: remove CONFIG_CLKDEV_LOOKUP 2021-06-08T15:00:09+00:00 Arnd Bergmann arnd@arndb.de 2021-05-31T09:48:49+00:00 2f4574dd6dd19eb3e8ab0415a3ae960d04be3a65 This option is now synonymous with CONFIG_HAVE_CLK, so use the latter globally. Any out-of-tree platform ports that still use a private clk_get()/clk_put() implementation should move to CONFIG_COMMON_CLK. Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
This option is now synonymous with CONFIG_HAVE_CLK, so use
the latter globally. Any out-of-tree platform ports that
still use a private clk_get()/clk_put() implementation should
move to CONFIG_COMMON_CLK.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2021-04-29T00:13:56+00:00 Linus Torvalds torvalds@linux-foundation.org 2021-04-29T00:13:56+00:00 35655ceb31b56cd1cb52635a725dfcdb9662d7b7 Pull clk updates from Stephen Boyd: "Here's a collection of largely clk driver updates. The usual suspects are here: i.MX, Qualcomm, Renesas, Allwinner, Samsung, and Rockchip, but it feels pretty light on commits. There's only one real commit to the framework core and that's to consolidate code. Otherwise the diffstat is dominated by many Qualcomm clk driver patches that modernize the driver for the proper way of speciying clk parents. That's shifting data around, which could subtly break things so I'll be on the lookout for fixes. New Drivers: - Proper clk driver for Mediatek MT7621 SoCs - Support for the clock controller on the new Rockchip rk3568 Updates: - Simplify Zynq Kconfig dependencies - Use clk_hw pointers in socfpga driver - Cleanup parent data in qcom clk drivers - Some cleanups for rk3399 modularization - Fix reparenting of i.MX UART clocks by initializing only the ones associated to stdout - Correct the PCIE clocks for i.MX8MP and i.MX8MQ - Make i.MX LPCG and SCU clocks return on registering failure - Kernel doc fixes - Add DAB hardware accelerator clocks on Renesas R-Car E3 and M3-N - Add timer (TMU) clocks on Renesas R-Car H3 ES1.0 - Add Timer (TMU & CMT) and thermal sensor (TSC) clocks on Renesas R-Car V3U - Sigma-delta modulation on Allwinner V3s audio PLL" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (82 commits) MAINTAINERS: add MT7621 CLOCK maintainer staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' staging: mt7621-dts: make use of new 'mt7621-clk' clk: ralink: add clock driver for mt7621 SoC clk: uniphier: Fix potential infinite loop clk: qcom: rpmh: add support for SDX55 rpmh IPA clock clk: qcom: gcc-sdm845: get rid of the test clock clk: qcom: convert SDM845 Global Clock Controller to parent_data dt-bindings: clock: separate SDM845 GCC clock bindings clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE dt: bindings: add mt7621-sysc device tree binding documentation dt-bindings: clock: add dt binding header for mt7621 clocks clk: samsung: Remove redundant dev_err calls clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback clk: zynqmp: Drop dependency on ARCH_ZYNQMP clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents ... 
Pull clk updates from Stephen Boyd:
 "Here's a collection of largely clk driver updates. The usual suspects
  are here: i.MX, Qualcomm, Renesas, Allwinner, Samsung, and Rockchip,
  but it feels pretty light on commits.

  There's only one real commit to the framework core and that's to
  consolidate code. Otherwise the diffstat is dominated by many Qualcomm
  clk driver patches that modernize the driver for the proper way of
  speciying clk parents. That's shifting data around, which could subtly
  break things so I'll be on the lookout for fixes.

  New Drivers:
   - Proper clk driver for Mediatek MT7621 SoCs
   - Support for the clock controller on the new Rockchip rk3568

  Updates:
   - Simplify Zynq Kconfig dependencies
   - Use clk_hw pointers in socfpga driver
   - Cleanup parent data in qcom clk drivers
   - Some cleanups for rk3399 modularization
   - Fix reparenting of i.MX UART clocks by initializing only the ones
     associated to stdout
   - Correct the PCIE clocks for i.MX8MP and i.MX8MQ
   - Make i.MX LPCG and SCU clocks return on registering failure
   - Kernel doc fixes
   - Add DAB hardware accelerator clocks on Renesas R-Car E3 and M3-N
   - Add timer (TMU) clocks on Renesas R-Car H3 ES1.0
   - Add Timer (TMU & CMT) and thermal sensor (TSC) clocks on
     Renesas R-Car V3U
   - Sigma-delta modulation on Allwinner V3s audio PLL"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (82 commits)
  MAINTAINERS: add MT7621 CLOCK maintainer
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
  staging: mt7621-dts: make use of new 'mt7621-clk'
  clk: ralink: add clock driver for mt7621 SoC
  clk: uniphier: Fix potential infinite loop
  clk: qcom: rpmh: add support for SDX55 rpmh IPA clock
  clk: qcom: gcc-sdm845: get rid of the test clock
  clk: qcom: convert SDM845 Global Clock Controller to parent_data
  dt-bindings: clock: separate SDM845 GCC clock bindings
  clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE
  dt: bindings: add mt7621-sysc device tree binding documentation
  dt-bindings: clock: add dt binding header for mt7621 clocks
  clk: samsung: Remove redundant dev_err calls
  clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
  clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
  clk: zynqmp: Drop dependency on ARCH_ZYNQMP
  clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
  clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents
  ...
clk: ralink: add clock driver for mt7621 SoC 2021-04-13T02:10:54+00:00 Sergio Paracuellos sergio.paracuellos@gmail.com 2021-04-10T05:50:56+00:00 48df7a26f4700aac8b7e5ab68796daf25c27e062 The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. Looking into driver code, and some openWRT patched there are another frequencies which are used in some drivers (uart, sd...). According to all of this information the clock plan for this SoC is set as follows: - Main top clock "xtal" from where all the rest of the world is derived. - CPU clock "cpu" derived from "xtal" frequencies and a bunch of register reads and predividers. - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz. - Fixed clocks from "xtal": * "50m": 50 MHz. * "125m": 125 MHz. * "150m": 150 MHz. * "250m": 250 MHz. * "270m": 270 MHz. We also have a buch of gate clocks with their parents: * "hsdma": "150m" * "fe": "250m" * "sp_divtx": "270m" * "timer": "50m" * "pcm": "270m" * "pio": "50m" * "gdma": "bus" * "nand": "125m" * "i2c": "50m" * "i2s": "270m" * "spi": "bus" * "uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m" * "shxc": "50m" With this information the clk driver will provide clock and gates functionality from a a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210410055059.13518-2-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
    * "50m": 50 MHz.
    * "125m": 125 MHz.
    * "150m": 150 MHz.
    * "250m": 250 MHz.
    * "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210410055059.13518-2-sergio.paracuellos@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: socfpga: allow building N5X clocks with ARCH_N5X 2021-03-23T16:03:35+00:00 Krzysztof Kozlowski krzysztof.kozlowski@canonical.com 2021-03-11T15:25:31+00:00 3b218baa744b0c7161d1784414e0a9db6bc9bf6b The Intel's eASIC N5X (ARCH_N5X) architecture shares a lot with Agilex (ARCH_AGILEX) so it uses the same socfpga_agilex.dtsi, with minor changes. Also the clock drivers are the same. However the clock drivers won't be build without ARCH_AGILEX. One could assume that ARCH_N5X simply depends on ARCH_AGILEX but this was not modeled in Kconfig. In current stage the ARCH_N5X is simply unbootable. Add a separate Kconfig entry for clocks used by both ARCH_N5X and ARCH_AGILEX so the necessary objects will be built if either of them is selected. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 
The Intel's eASIC N5X (ARCH_N5X) architecture shares a lot with Agilex
(ARCH_AGILEX) so it uses the same socfpga_agilex.dtsi, with minor
changes.  Also the clock drivers are the same.

However the clock drivers won't be build without ARCH_AGILEX.  One could
assume that ARCH_N5X simply depends on ARCH_AGILEX but this was not
modeled in Kconfig.  In current stage the ARCH_N5X is simply
unbootable.

Add a separate Kconfig entry for clocks used by both ARCH_N5X and
ARCH_AGILEX so the necessary objects will be built if either of them is
selected.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>