linux.git/drivers/clk/Kconfig, branch v3.15

Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux

2014-04-06T01:39:18+00:00

Pull clock framework changes from Mike Turquette:
 "The clock framework changes for 3.15 look similar to past pull
  requests.  Mostly clock driver updates, more Device Tree support in
  the form of common functions useful across platforms and a handful of
  features and fixes to the framework core"

* tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: shmobile: fix setting paretn clock rate
  clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
  clk: Fix minor errors in of_clk_init() function comments
  clk: reverse default clk provider initialization order in of_clk_init()
  clk: sirf: update copyright years to 2014
  clk: mmp: try to use closer one when do round rate
  clk: mmp: fix the wrong calculation formula
  clk: mmp: fix wrong mask when calculate denominator
  clk: st: Adds quadfs clock binding
  clk: st: Adds clockgen-vcc and clockgen-mux clock binding
  clk: st: Adds clockgen clock binding
  clk: st: Adds divmux and prediv clock binding
  clk: st: Support for A9 MUX clocks
  clk: st: Support for ClockGenA9/DDR/GPU
  clk: st: Support for QUADFS inside ClockGenB/C/D/E/F
  clk: st: Support for VCC-mux and MUX clocks
  clk: st: Support for PLLs inside ClockGenA(s)
  clk: st: Support for DIVMUX and PreDiv Clocks
  clk: support hardware-specific debugfs entries
  clk: s2mps11: Use of_get_child_by_name
  ...

clk: clk-s2mps11: Add support for clocks in S5M8767 MFD

2014-03-19T00:13:24+00:00

Since clock operation within S2MPS11 and S5M8767 are similar, we can
support both the devices within a single driver.

Signed-off-by: Tushar Behera 
Reviewed-by: Tomasz Figa 
Reviewed-by: Yadwinder Singh Brar 
Signed-off-by: Mike Turquette

clk: bcm281xx: add initial clock framework support

2014-02-24T18:43:46+00:00

Add code for device tree support of clocks in the BCM281xx family of
SoCs.  Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs).  (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)

A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC.  A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers.  There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more).  There are also "fractional" dividers which allow
division by non-integer values.  To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.

If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed.  The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.

The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock.  Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate.  (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)

The source code is divided into three general portions:

    drivers/clk/bcm/clk-kona.h
    drivers/clk/bcm/clk-kona.c
        These implement the basic Kona clock functionality,
        including the clk_ops methods and various routines to
        manipulate registers and interpret their values.  This
        includes some functions used to set clocks to a desired
        initial state (though this feature is only partially
        implemented here).

    drivers/clk/bcm/clk-kona-setup.c
        This contains generic run-time initialization code for
        data structures representing Kona CCUs and clocks.  This
        encapsulates the clock structure initialization that can't
        be done statically.  Note that there is a great deal of
        validity-checking code here, making explicit certain
        assumptions in the code.   This is mostly useful for adding
        new clock definitions and could possibly be disabled for
        production use.

    drivers/clk/bcm/clk-bcm281xx.c
        This file defines the specific CCUs used by BCM281XX family
        SoCs, as well as the specific clocks implemented by each.
        It declares a device tree clock match entry for each CCU
        defined.

    include/dt-bindings/clock/bcm281xx.h
        This file defines the selector (index) values used to
        identify a particular clock provided by a CCU.  It consists
        entirely of C preprocessor constants, to be used by both the
        C source and device tree source files.

Signed-off-by: Alex Elder 
Reviewed-by: Tim Kryger 
Reviewed-by: Matt Porter 
Acked-by: Mike Turquette 
Signed-off-by: Matt Porter

clk: qcom: Add a regmap type clock struct

2014-01-16T20:00:58+00:00

Add a clock type that associates a regmap pointer and some
enable/disable bits with a clk_hw struct. This will be the struct
that a hw specific implementation wraps if it wants to use the
regmap helper functions.

Signed-off-by: Stephen Boyd 
Signed-off-by: Mike Turquette

clk: remove CONFIG_COMMON_CLK_DEBUG

2013-12-28T01:45:08+00:00

Populate ${DEBUGS_MOUNT_POINT}/clk if CONFIG_DEBUG_FS is set. This
eliminates the extra (annoying) step of enabling the config option
manually.

Signed-off-by: Mike Turquette

clk: si570: Add a driver for SI570 oscillators

2013-12-15T05:01:35+00:00

Add a driver for SILabs 570, 571, 598, 599 programmable oscillators.
The devices generate low-jitter clock signals and are reprogrammable via
an I2C interface.

Reviewed-by: Guenter Roeck 
Signed-off-by: Soren Brinkmann 
Signed-off-by: Mike Turquette

clk: keystone: Build Keystone clock drivers

2013-10-08T01:16:37+00:00

Now build the keystone common clock drivers. The build is made
conditional based on COMMON_CLK_KEYSTONE

Signed-off-by: Santosh Shilimkar 
Signed-off-by: Mike Turquette

clk: Add APM X-Gene SoC clock driver

2013-10-07T18:22:15+00:00

clk: Add APM X-Gene SoC clock driver for reference, PLL, and device clocks.

Signed-off-by: Loc Ho 
Signed-off-by: Kumar Sankaran 
Signed-off-by: Vinayak Kale 
Signed-off-by: Feng Kan 
Signed-off-by: Mike Turquette

clk: s2mps11: Add support for s2mps11

2013-08-08T22:57:33+00:00

This patch adds support to register three(AP/CP/BT) buffered 32.768 KHz
outputs of mfd-s2mps11 with common clock framework.

Signed-off-by: Yadwinder Singh Brar 
Signed-off-by: Mike Turquette

clk: fix typos

2013-07-25T21:06:11+00:00

Signed-off-by: Peter Meerwald 
Signed-off-by: Mike Turquette