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<title>linux.git/arch/xtensa/kernel/head.S, branch v5.1</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>xtensa: SMP: fix secondary CPU initialization</title>
<updated>2019-01-26T10:02:13+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-12-21T16:26:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=32a7726c4f4aadfabdb82440d84f88a5a2c8fe13'/>
<id>32a7726c4f4aadfabdb82440d84f88a5a2c8fe13</id>
<content type='text'>
- add missing memory barriers to the secondary CPU synchronization spin
  loops; add comment to the matching memory barrier in the boot_secondary
  and __cpu_die functions;
- use READ_ONCE/WRITE_ONCE to access cpu_start_id/cpu_start_ccount
  instead of reading/writing them directly;
- re-initialize cpu_running every time before starting secondary CPU to
  flush possible previous CPU startup results.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- add missing memory barriers to the secondary CPU synchronization spin
  loops; add comment to the matching memory barrier in the boot_secondary
  and __cpu_die functions;
- use READ_ONCE/WRITE_ONCE to access cpu_start_id/cpu_start_ccount
  instead of reading/writing them directly;
- re-initialize cpu_running every time before starting secondary CPU to
  flush possible previous CPU startup results.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: don't use l32r opcode directly</title>
<updated>2018-12-05T20:53:07+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-12-05T20:48:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=037602705109ec2ab96340bea93ad87daa3ac046'/>
<id>037602705109ec2ab96340bea93ad87daa3ac046</id>
<content type='text'>
xtensa assembler is capable of representing register loads with either
movi + addmi, l32r or const16, depending on the core configuration.
Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let
the assembler relax them.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
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<pre>
xtensa assembler is capable of representing register loads with either
movi + addmi, l32r or const16, depending on the core configuration.
Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let
the assembler relax them.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: fix boot parameters address translation</title>
<updated>2018-11-14T08:15:32+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-11-14T07:46:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=40dc948f234b73497c3278875eb08a01d5854d3f'/>
<id>40dc948f234b73497c3278875eb08a01d5854d3f</id>
<content type='text'>
The bootloader may pass physical address of the boot parameters structure
to the MMUv3 kernel in the register a2. Code in the _SetupMMU block in
the arch/xtensa/kernel/head.S is supposed to map that physical address to
the virtual address in the configured virtual memory layout.

This code haven't been updated when additional 256+256 and 512+512
memory layouts were introduced and it may produce wrong addresses when
used with these layouts.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
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<pre>
The bootloader may pass physical address of the boot parameters structure
to the MMUv3 kernel in the register a2. Code in the _SetupMMU block in
the arch/xtensa/kernel/head.S is supposed to map that physical address to
the virtual address in the configured virtual memory layout.

This code haven't been updated when additional 256+256 and 512+512
memory layouts were introduced and it may produce wrong addresses when
used with these layouts.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: rework noMMU cache attributes initialization</title>
<updated>2018-08-14T03:08:19+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-08-12T13:01:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7bb516ca5424e12b42124fab2906b6da9c81ba9c'/>
<id>7bb516ca5424e12b42124fab2906b6da9c81ba9c</id>
<content type='text'>
Marking default memory region as cached is not always sufficient and is
not flexible. Allow specifying cache attributes for the whole memory
address space with new config entry MEMMAP_CACHEATTR. Apply it after
cache initialization.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
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<pre>
Marking default memory region as cached is not always sufficient and is
not flexible. Allow specifying cache attributes for the whole memory
address space with new config entry MEMMAP_CACHEATTR. Apply it after
cache initialization.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: use call instead of callx in assembly code</title>
<updated>2017-12-10T22:48:52+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2017-12-10T02:44:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2da03d4114b2587f0e8e45f4862074e34daee64e'/>
<id>2da03d4114b2587f0e8e45f4862074e34daee64e</id>
<content type='text'>
Now that xtensa assembly sources are compiled with -mlongcalls let the
assembler and linker relax call instructions into l32r + callx where
needed. This change makes the code cleaner and potentially a bit faster.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now that xtensa assembly sources are compiled with -mlongcalls let the
assembler and linker relax call instructions into l32r + callx where
needed. This change makes the code cleaner and potentially a bit faster.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: cleanup MMU setup and kernel layout macros</title>
<updated>2016-07-24T03:33:58+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-04-13T02:20:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a9f2fc628e3a26a829fd79aff74eb49839d1e74b'/>
<id>a9f2fc628e3a26a829fd79aff74eb49839d1e74b</id>
<content type='text'>
Make kernel load address explicit, independent of the selected MMU
configuration and configurable from Kconfig. Do not restrict it to the
first 512MB of the physical address space.

Cleanup kernel memory layout macros:

- rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
- drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
- introduce PHYS_OFFSET and use it in __va and __pa definitions;
- synchronize MMU/noMMU vectors, drop unused NMI vector;
- replace hardcoded vectors offset of 0x3000 with Kconfig symbol.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make kernel load address explicit, independent of the selected MMU
configuration and configurable from Kconfig. Do not restrict it to the
first 512MB of the physical address space.

Cleanup kernel memory layout macros:

- rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
- drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
- introduce PHYS_OFFSET and use it in __va and __pa definitions;
- synchronize MMU/noMMU vectors, drop unused NMI vector;
- replace hardcoded vectors offset of 0x3000 with Kconfig symbol.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: use context structure for debug exceptions</title>
<updated>2016-03-11T08:53:32+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-03-06T22:36:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6ec7026ac01f3db039e0428db1f37590685ad3e7'/>
<id>6ec7026ac01f3db039e0428db1f37590685ad3e7</id>
<content type='text'>
With implementation of data breakpoints debug exceptions raised when
PS.EXCM is set need to be handled, e.g. window overflow code can write
to watched userspace address. Currently debug exception handler uses
EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be
available when PS.EXCM is set and more space will be needed to save
additional state.
Reorganize debug context: create per-CPU structure debug_table instance
and store its address in the EXCSAVE&lt;debug level&gt; instead of
debug_exception function address. Expand this structure when more save
space is needed.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With implementation of data breakpoints debug exceptions raised when
PS.EXCM is set need to be handled, e.g. window overflow code can write
to watched userspace address. Currently debug exception handler uses
EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be
available when PS.EXCM is set and more space will be needed to save
additional state.
Reorganize debug context: create per-CPU structure debug_table instance
and store its address in the EXCSAVE&lt;debug level&gt; instead of
debug_exception function address. Expand this structure when more save
space is needed.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: clear all DBREAKC registers on start</title>
<updated>2016-03-11T08:53:32+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-03-03T15:34:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7de7ac785ae18a2cdc78d7560f48e3213d9ea0ab'/>
<id>7de7ac785ae18a2cdc78d7560f48e3213d9ea0ab</id>
<content type='text'>
There are XCHAL_NUM_DBREAK registers, clear them all.
This also fixes cryptic assembler error message with binutils 2.25 when
XCHAL_NUM_DBREAK is 0:

  as: out of memory allocating 18446744073709551575 bytes after a total
  of 495616 bytes

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There are XCHAL_NUM_DBREAK registers, clear them all.
This also fixes cryptic assembler error message with binutils 2.25 when
XCHAL_NUM_DBREAK is 0:

  as: out of memory allocating 18446744073709551575 bytes after a total
  of 495616 bytes

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: fixes for configs without loop option</title>
<updated>2015-11-02T15:02:47+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2015-09-24T20:11:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5029615e25dc5040beb065f36743c127a8e51497'/>
<id>5029615e25dc5040beb065f36743c127a8e51497</id>
<content type='text'>
Build-time fixes:
- make lbeg/lend/lcount save/restore conditional on kernel entry;
- don't clear lcount in platform_restart functions unconditionally.

Run-time fixes:
- use correct end of range register in __endla paired with __loopt, not
  the unused temporary register. This fixes .bss zero-initialization.
  Update comments in asmmacro.h;
- don't clobber a10 in the usercopy that leads to access to unmapped
  memory.

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Build-time fixes:
- make lbeg/lend/lcount save/restore conditional on kernel entry;
- don't clear lcount in platform_restart functions unconditionally.

Run-time fixes:
- use correct end of range register in __endla paired with __loopt, not
  the unused temporary register. This fixes .bss zero-initialization.
  Update comments in asmmacro.h;
- don't clobber a10 in the usercopy that leads to access to unmapped
  memory.

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: move vecbase SR initialization to _startup</title>
<updated>2014-10-21T09:28:55+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2014-10-04T01:12:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=53490121e9ffa3e6314137af016cde8ac83c9bb4'/>
<id>53490121e9ffa3e6314137af016cde8ac83c9bb4</id>
<content type='text'>
Instead of initializing vecbase in initialize_mmu macro, which may be
expanded either in Image.elf reset vector hadler or in the kernel
head.S, both times only when CONFIG_MMU is enabled, do this
initialization once in _startup function.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Instead of initializing vecbase in initialize_mmu macro, which may be
expanded either in Image.elf reset vector hadler or in the kernel
head.S, both times only when CONFIG_MMU is enabled, do this
initialization once in _startup function.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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