linux.git/arch/xtensa/kernel/entry.S, branch v3.12-rc2

xtensa: new fast_alloca handler

2013-09-06T16:48:12+00:00

Instead of emulating movsp instruction in the kernel use window
underflow handler to load missing register window and retry failed
movsp.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: keep a3 and excsave1 on entry to exception handlers

2013-09-06T16:47:41+00:00

Based on the SMP patch by Joe Taylor and subsequent fixes.
Preserve exception table pointer (normally stored in excsave1 SR) as it
cannot be easily restored in SMP environment.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: enable kernel preemption

2013-09-06T16:46:49+00:00

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: check thread flags atomically on return from user exception

2013-09-06T16:46:35+00:00

Check pending signals and rescheduling thread flags with interrupts
disabled, and don't enable them if no flags are set. Call
trace_hardirqs_on after thread flags handling, so that rescheduling is
done and hardirqs tracking flag is updated in the correct task context.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: check TLB sanity on return to userspace

2013-07-08T08:18:56+00:00

- check that user TLB mappings correspond to the current page table;
- check that TLB mapping VPN is in the kernel/user address range
  in accordance with its ASID.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: fix fast_store_prohibited _PAGE_WRITABLE_BIT test

2013-05-20T18:48:23+00:00

Before _PAGE_WRITABLE_BIT test fast_store_prohibited must make sure that
PTE is present. Otherwise 'writable' bit is undefined and may be reused
in the 'file offset' or 'swap type' PTE fields.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: disable IRQs while IRQ handler is running

2013-05-09T08:07:11+00:00

IRQ handlers are expected to run with IRQs disabled.
See e.g. http://lwn.net/Articles/380931/ for a longer story.

This was overlooked in the commit
  2d1c645 xtensa: dispatch medium-priority interrupts
Revert to old behavior and simplify interrupt entry and exit code.
Interrupt handler still honours IRQ priority.

do_notify_resume/schedule must be called with interrupts enabled, enable
interrupts if we return from user exception.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add irq flags trace support

2013-05-09T08:07:11+00:00

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add support for TLS

2013-02-24T03:35:57+00:00

The Xtensa architecture provides a global register called THREADPTR
for the purpose of Thread Local Storage (TLS) support. This allows us
to use a fairly simple implementation, keeping the thread pointer in
the regset and simply saving and restoring it upon entering/exiting
the from user space.

Signed-off-by: Chris Zankel

xtensa: add support for oprofile

2013-02-24T03:22:54+00:00

Support call graph profiling.
Keep upper two bits of PC unchanged through backtrace rather than take
them from sp (a1). The stack pointer is usually in the same GB (same
upper 2 bits) as PC, but technically doesn't always have to be (and
might not in the future, when taking full advantage of MMU v3).

Signed-off-by: Dan Nicolaescu 
Signed-off-by: Pete Delaney 
Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel