linux.git/arch/xtensa/include/asm/core.h, branch v6.2 Linux kernel source tree xtensa: merge stack alignment definitions 2022-03-19T20:08:11+00:00 Max Filippov jcmvbkbc@gmail.com 2022-03-19T18:06:30+00:00 e94dc6bbdf29787a5ddb01c143a074c31e427dc7 xtensa currently has two different definitions for stack alignment. Replace it with single definition usable in both C and assembly. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
xtensa currently has two different definitions for stack alignment.
Replace it with single definition usable in both C and assembly.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: definitions for call0 ABI 2021-10-19T05:19:34+00:00 Max Filippov jcmvbkbc@gmail.com 2021-05-01T22:30:06+00:00 5cce39b6aaa02da77e071b2b0880bedfb903330f Add assembly macros for calls, call arguments, preserved registers, function entry and return for windowed and call0 ABIs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
Add assembly macros for calls, call arguments, preserved registers,
function entry and return for windowed and call0 ABIs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: clean up optional XCHAL_* definitions 2020-02-01T08:43:28+00:00 Max Filippov jcmvbkbc@gmail.com 2020-02-01T05:20:58+00:00 a922b1561137fc516e7c77c478779f7d198cc9cf Simplify users of XCHAL_HAVE_EXTERN_REGS and XCHAL_HAVE_VECBASE and always define them as 0 if they're not defined in the variant/core.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
Simplify users of XCHAL_HAVE_EXTERN_REGS and XCHAL_HAVE_VECBASE and
always define them as 0 if they're not defined in the variant/core.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: implement initialize_cacheattr for MPU cores 2019-05-07T17:36:34+00:00 Max Filippov jcmvbkbc@gmail.com 2019-05-06T23:47:41+00:00 a5944195d00a359e28d6e093593609bcee37ed5e Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa LSP RM document. Coalesce adjacent regions with the same cacheattr. Update Kconfig help text. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa
LSP RM document. Coalesce adjacent regions with the same cacheattr.
Update Kconfig help text.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: add exclusive atomics support 2019-05-07T17:36:31+00:00 Max Filippov jcmvbkbc@gmail.com 2018-12-21T01:18:12+00:00 f7c34874f04a80d6c39a32f08da2529e59602d3c Implement atomic primitives using exclusive access opcodes available in the recent xtensa cores. Since l32ex/s32ex don't have any memory ordering guarantees don't define __smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: replace variant/core.h with asm/core.h 2019-05-07T00:48:55+00:00 Max Filippov jcmvbkbc@gmail.com 2019-01-02T03:41:55+00:00 8f8d5745bb520c76b81abef4a2cb3023d0313bfd Introduce the header arch/xtensa/include/asm/core.h that provides definitions for XCHAL macros missing in older xtensa releases. Use this header instead of variant/core.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>