Pull Xtensa updates from Max Filippov:

 - clean up bootable image build targets: provide separate 'Image',
   'zImage' and 'uImage' make targets that only build corresponding
   image type. Make 'all' build all images appropriate for a platform

 - allow merging vectors code into .text section as a preparation step
   for XIP support

 - fix handling external FDT when the kernel is built without
   BLK_DEV_INITRD support

* tag 'xtensa-20170303' of git://github.com/jcmvbkbc/linux-xtensa:
  xtensa: allow merging vectors into .text section
  xtensa: clean up bootable image build targets
  xtensa: move parse_tag_fdt out of #ifdef CONFIG_BLK_DEV_INITRD

Currently xtensa uses 'zImage' as a synonym of 'all', but in fact xtensa
supports three targets: 'Image' (ELF image with reset vector), 'zImage'
(compressed redboot image) and 'uImage' (U-Boot image).
Provide separate 'Image', 'zImage' and 'uImage' make targets that only
build corresponding image type. Make 'all' build all images appropriate
for a platform.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Add example 64MByte long reservation in the first 512MBytes of physical
memory used as shared DMA pool.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

DT-enabled kernel should have a CPU node connected to a clock. This clock
is the CCOUNT clock. Use old platform_calibrate_ccount call as a fallback
when CPU node cannot be found or has no clock and in non-DT-enabled
configurations.

Drop no longer needed code that updates CPU clock-frequency property in
the DT; drop DT-related code from the platform_calibrate_ccount too.

Move of_clk_init to the top of time_init, so that clocks are initialized
before CCOUNT calibration is attempted.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Instead of querying hardcoded FPGA frequency register and then updating
clock-frequency property in specificly named DT nodes in machine setup
code register a clock provider that returns fixed-rate clock, configured
by register specified in DT. This way we have less magic/hardcoded names
and use more existing common clock framework code.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>

Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Added defconfig, device tree and Xtensa variant header files for the
Cadence Configurable System Platform "xt_lnx" processor configuration.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Make kernel load address explicit, independent of the selected MMU
configuration and configurable from Kconfig. Do not restrict it to the
first 512MB of the physical address space.

Cleanup kernel memory layout macros:

- rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
- drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
- introduce PHYS_OFFSET and use it in __va and __pa definitions;
- synchronize MMU/noMMU vectors, drop unused NMI vector;
- replace hardcoded vectors offset of 0x3000 with Kconfig symbol.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Serial port is attached to XTFPGA boards as native endian device, now
that earlycon parameter parser understands mmio32native put it into
earlycon kernel parameter. This makes early console functional on both
little- and big-endian CPUs with identical kernel command lines.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

I2C controller is attached to XTFPGA boards as native endian device, mark
it as such in DTS.
Set register width in DTS to 4, this way it works both for little- and
big-endian CPUs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>