linux.git/arch/x86/kernel/cpu/resctrl/ctrlmondata.c, branch v6.8

x86/resctrl: Enable non-contiguous CBMs in Intel CAT

2023-10-11T19:48:52+00:00

The setting for non-contiguous 1s support in Intel CAT is
hardcoded to false. On these systems, writing non-contiguous
1s into the schemata file will fail before resctrl passes
the value to the hardware.

In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped
being reserved and now carry information about non-contiguous 1s
value support for L3 and L2 cache respectively. The CAT
capacity bitmask (CBM) supports a non-contiguous 1s value if
the bit is set.

The exception are Haswell systems where non-contiguous 1s value
support needs to stay disabled since they can't make use of CPUID
for Cache allocation.

Originally-by: Fenghua Yu 
Signed-off-by: Maciej Wieczor-Retman 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Ilpo Järvinen 
Reviewed-by: Peter Newman 
Reviewed-by: Reinette Chatre 
Reviewed-by: Babu Moger 
Tested-by: Peter Newman 
Link: https://lore.kernel.org/r/1849b487256fe4de40b30f88450cba3d9abc9171.1696934091.git.maciej.wieczor-retman@intel.com

x86/resctrl: Rename arch_has_sparse_bitmaps

2023-10-11T17:43:43+00:00

Rename arch_has_sparse_bitmaps to arch_has_sparse_bitmasks to ensure
consistent terminology throughout resctrl.

Suggested-by: Reinette Chatre 
Signed-off-by: Maciej Wieczor-Retman 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Ilpo Järvinen 
Reviewed-by: Peter Newman 
Reviewed-by: Reinette Chatre 
Reviewed-by: Babu Moger 
Tested-by: Peter Newman 
Link: https://lore.kernel.org/r/e330fcdae873ef1a831e707025a4b70fa346666e.1696934091.git.maciej.wieczor-retman@intel.com

x86/resctrl: Clear staged_config[] before and after it is used

2023-03-15T22:19:43+00:00

As a temporary storage, staged_config[] in rdt_domain should be cleared
before and after it is used. The stale value in staged_config[] could
cause an MSR access error.

Here is a reproducer on a system with 16 usable CLOSIDs for a 15-way L3
Cache (MBA should be disabled if the number of CLOSIDs for MB is less than
16.) :
	mount -t resctrl resctrl -o cdp /sys/fs/resctrl
	mkdir /sys/fs/resctrl/p{1..7}
	umount /sys/fs/resctrl/
	mount -t resctrl resctrl /sys/fs/resctrl
	mkdir /sys/fs/resctrl/p{1..8}

An error occurs when creating resource group named p8:
    unchecked MSR access error: WRMSR to 0xca0 (tried to write 0x00000000000007ff) at rIP: 0xffffffff82249142 (cat_wrmsr+0x32/0x60)
    Call Trace:
     
     __flush_smp_call_function_queue+0x11d/0x170
     __sysvec_call_function+0x24/0xd0
     sysvec_call_function+0x89/0xc0
     
     
     asm_sysvec_call_function+0x16/0x20

When creating a new resource control group, hardware will be configured
by the following process:
    rdtgroup_mkdir()
      rdtgroup_mkdir_ctrl_mon()
        rdtgroup_init_alloc()
          resctrl_arch_update_domains()

resctrl_arch_update_domains() iterates and updates all resctrl_conf_type
whose have_new_ctrl is true. Since staged_config[] holds the same values as
when CDP was enabled, it will continue to update the CDP_CODE and CDP_DATA
configurations. When group p8 is created, get_config_index() called in
resctrl_arch_update_domains() will return 16 and 17 as the CLOSIDs for
CDP_CODE and CDP_DATA, which will be translated to an invalid register -
0xca0 in this scenario.

Fix it by clearing staged_config[] before and after it is used.

[reinette: re-order commit tags]

Fixes: 75408e43509e ("x86/resctrl: Allow different CODE/DATA configurations to be staged")
Suggested-by: Xin Hao 
Signed-off-by: Shawn Wang 
Signed-off-by: Reinette Chatre 
Signed-off-by: Dave Hansen 
Tested-by: Reinette Chatre 
Cc:stable@vger.kernel.org
Link: https://lore.kernel.org/all/2fad13f49fbe89687fc40e9a5a61f23a28d1507a.1673988935.git.reinette.chatre%40intel.com

x86/resctrl: Detect and configure Slow Memory Bandwidth Allocation

2023-01-23T16:38:44+00:00

The QoS slow memory configuration details are available via
CPUID_Fn80000020_EDX_x02. Detect the available details and
initialize the rest to defaults.

Signed-off-by: Babu Moger 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Reinette Chatre 
Link: https://lore.kernel.org/r/20230113152039.770054-7-babu.moger@amd.com

x86/resctrl: Replace smp_call_function_many() with on_each_cpu_mask()

2023-01-23T16:38:04+00:00

on_each_cpu_mask() runs the function on each CPU specified by cpumask,
which may include the local processor.

Replace smp_call_function_many() with on_each_cpu_mask() to simplify
the code.

Signed-off-by: Babu Moger 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Reinette Chatre 
Link: https://lore.kernel.org/r/20230113152039.770054-2-babu.moger@amd.com

x86/resctrl: Remove arch_has_empty_bitmaps

2022-10-24T08:30:29+00:00

The field arch_has_empty_bitmaps is not required anymore. The field
min_cbm_bits is enough to validate the CBM (capacity bit mask) if the
architecture can support the zero CBM or not.

Suggested-by: Reinette Chatre 
Signed-off-by: Babu Moger 
Signed-off-by: Borislav Petkov 
Reviewed-by: Reinette Chatre 
Reviewed-by: Fenghua Yu 
Link: https://lore.kernel.org/r/166430979654.372014.615622285687642644.stgit@bmoger-ubuntu

x86/resctrl: Make resctrl_arch_rmid_read() return values in bytes

2022-09-23T12:25:05+00:00

resctrl_arch_rmid_read() returns a value in chunks, as read from the
hardware. This needs scaling to bytes by mon_scale, as provided by
the architecture code.

Now that resctrl_arch_rmid_read() performs the overflow and corrections
itself, it may as well return a value in bytes directly. This allows
the accesses to the architecture specific 'hw' structure to be removed.

Move the mon_scale conversion into resctrl_arch_rmid_read().
mbm_bw_count() is updated to calculate bandwidth from bytes.

Signed-off-by: James Morse 
Signed-off-by: Borislav Petkov 
Reviewed-by: Jamie Iles 
Reviewed-by: Shaopeng Tan 
Reviewed-by: Reinette Chatre 
Tested-by: Xin Hao 
Tested-by: Shaopeng Tan 
Tested-by: Cristian Marussi 
Link: https://lore.kernel.org/r/20220902154829.30399-22-james.morse@arm.com

x86/resctrl: Abstract __rmid_read()

2022-09-23T12:17:20+00:00

__rmid_read() selects the specified eventid and returns the counter
value from the MSR. The error handling is architecture specific, and
handled by the callers, rdtgroup_mondata_show() and __mon_event_count().

Error handling should be handled by architecture specific code, as
a different architecture may have different requirements. MPAM's
counters can report that they are 'not ready', requiring a second
read after a short delay. This should be hidden from resctrl.

Make __rmid_read() the architecture specific function for reading
a counter. Rename it resctrl_arch_rmid_read() and move the error
handling into it.

A read from a counter that hardware supports but resctrl does not
now returns -EINVAL instead of -EIO from the default case in
__mon_event_count(). It isn't possible for user-space to see this
change as resctrl doesn't expose counters it doesn't support.

Signed-off-by: James Morse 
Signed-off-by: Borislav Petkov 
Reviewed-by: Jamie Iles 
Reviewed-by: Shaopeng Tan 
Reviewed-by: Reinette Chatre 
Tested-by: Xin Hao 
Tested-by: Shaopeng Tan 
Tested-by: Cristian Marussi 
Link: https://lore.kernel.org/r/20220902154829.30399-16-james.morse@arm.com

x86/resctrl: Allow update_mba_bw() to update controls directly

2022-09-22T15:43:44+00:00

update_mba_bw() calculates a new control value for the MBA resource
based on the user provided mbps_val and the current measured
bandwidth. Some control values need remapping by delay_bw_map().

It does this by calling wrmsrl() directly. This needs splitting
up to be done by an architecture specific helper, so that the
remainder can eventually be moved to /fs/.

Add resctrl_arch_update_one() to apply one configuration value
to the provided resource and domain. This avoids the staging
and cross-calling that is only needed with changes made by
user-space. delay_bw_map() moves to be part of the arch code,
to maintain the 'percentage control' view of MBA resources
in resctrl.

Signed-off-by: James Morse 
Signed-off-by: Borislav Petkov 
Reviewed-by: Jamie Iles 
Reviewed-by: Shaopeng Tan 
Reviewed-by: Reinette Chatre 
Tested-by: Xin Hao 
Tested-by: Shaopeng Tan 
Tested-by: Cristian Marussi 
Link: https://lore.kernel.org/r/20220902154829.30399-12-james.morse@arm.com

x86/resctrl: Switch over to the resctrl mbps_val list

2022-09-22T15:34:08+00:00

Updates to resctrl's software controller follow the same path as
other configuration updates, but they don't modify the hardware state.
rdtgroup_schemata_write() uses parse_line() and the resource's
parse_ctrlval() function to stage the configuration.
resctrl_arch_update_domains() then updates the mbps_val[] array
instead, and resctrl_arch_update_domains() skips the rdt_ctrl_update()
call that would update hardware.

This complicates the interface between resctrl's filesystem parts
and architecture specific code. It should be possible for mba_sc
to be completely implemented by the filesystem parts of resctrl. This
would allow it to work on a second architecture with no additional code.
resctrl_arch_update_domains() using the mbps_val[] array prevents this.

Change parse_bw() to write the configuration value directly to the
mbps_val[] array in the domain structure. Change rdtgroup_schemata_write()
to skip the call to resctrl_arch_update_domains(), meaning all the
mba_sc specific code in resctrl_arch_update_domains() can be removed.
On the read-side, show_doms() and update_mba_bw() are changed to read
the mbps_val[] array from the domain structure. With this,
resctrl_arch_get_config() no longer needs to consider mba_sc resources.

Signed-off-by: James Morse 
Signed-off-by: Borislav Petkov 
Reviewed-by: Jamie Iles 
Reviewed-by: Shaopeng Tan 
Reviewed-by: Reinette Chatre 
Tested-by: Xin Hao 
Tested-by: Shaopeng Tan 
Tested-by: Cristian Marussi 
Link: https://lore.kernel.org/r/20220902154829.30399-10-james.morse@arm.com