linux.git/arch/x86/kernel/cpu/perf_event_amd.c, branch v3.2

perf, x86: Share IBS macros between perf and oprofile

2011-10-10T04:57:11+00:00

Moving IBS macros from oprofile to  to make it
available to perf. No additional changes.

Signed-off-by: Robert Richter 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1316597423-25723-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar

perf, amd: Use GO/HO bits in perf-ctr

2011-10-06T11:00:31+00:00

The AMD perf-counters support counting in guest or host-mode
only. Make use of that feature when user-space specified
guest/host-mode only counting.

Signed-off-by: Joerg Roedel 
Signed-off-by: Gleb Natapov 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1317816084-18026-3-git-send-email-gleb@redhat.com
Signed-off-by: Ingo Molnar

x86: Perf_event_amd.c needs

2011-09-27T17:55:09+00:00

Fix (rare) build error by adding  header file:

  arch/x86/kernel/cpu/perf_event_amd.c:350:2: error: 'BAD_APICID' undeclared (first use in this function)

Signed-off-by: Randy Dunlap 
Cc: Robert Richter 
Cc: Andre Przywara 
Cc: Stephen Rothwell 
Link: http://lkml.kernel.org/r/4E820138.90301@xenotime.net
Signed-off-by: Ingo Molnar

x86, perf: Clean up perf_event cpu code

2011-09-26T10:58:00+00:00

The CPU support for perf events on x86 was implemented via included C files
with #ifdefs.  Clean this up by creating a new header file and compiling
the vendor-specific files as needed.

Signed-off-by: Kevin Winchester 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1314747665-2090-1-git-send-email-kjwinchester@gmail.com
Signed-off-by: Ingo Molnar

perf, x86: Avoid kfree() in CPU_STARTING

2011-08-14T09:53:02+00:00

On -rt kfree() can schedule, but CPU_STARTING is before the CPU is
fully up and running. These are contradictory, so avoid it. Instead
push the kfree() to CPU_ONLINE where we're free to schedule.

Reported-by: Thomas Gleixner 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/n/tip-kwd4j6ayld5thrscvaxgjquv@git.kernel.org
Signed-off-by: Ingo Molnar

perf, arch: Add generic NODE cache events

2011-07-01T09:06:38+00:00

Add a NODE level to the generic cache events which is used to measure
local vs remote memory accesses. Like all other cache events, an
ACCESS is HIT+MISS, if there is no way to distinguish between reads
and writes do reads only etc..

The below needs filling out for !x86 (which I filled out with
unsupported events).

I'm fairly sure ARM can leave it like that since it doesn't strike me as
an architecture that even has NUMA support. SH might have something since
it does appear to have some NUMA bits.

Sparc64, PowerPC and MIPS certainly want a good look there since they
clearly are NUMA capable.

Signed-off-by: Peter Zijlstra 
Cc: David Miller 
Cc: Anton Blanchard 
Cc: David Daney 
Cc: Deng-Cheng Zhu 
Cc: Paul Mundt 
Cc: Will Deacon 
Cc: Robert Richter 
Cc: Stephane Eranian 
Link: http://lkml.kernel.org/r/1303508226.4865.8.camel@laptop
Signed-off-by: Ingo Molnar

perf, x86: Add new stalled cycles events for Intel and AMD CPUs

2011-04-29T12:24:15+00:00

Extend the Intel and AMD event definitions with generic front-end and
back-end stall events.

( These are only approximations - suggestions are welcome for better events. )

Cc: Peter Zijlstra 
Cc: Arnaldo Carvalho de Melo 
Cc: Frederic Weisbecker 
Link: http://lkml.kernel.org/n/tip-7y40wib8n001io7hjpn1dsrm@git.kernel.org
Signed-off-by: Ingo Molnar

perf, x86: Fix AMD family 15h FPU event constraints

2011-04-19T08:07:55+00:00

Depending on the unit mask settings some FPU events may be scheduled
only on cpu counter #3. This patch fixes this.

Signed-off-by: Robert Richter 
Signed-off-by: Peter Zijlstra 
Cc: Stephane Eranian 
Link: http://lkml.kernel.org/r/1302913676-14352-3-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar

perf, x86: Fix pre-defined cache-misses event for AMD family 15h cpus

2011-04-19T08:07:54+00:00

With AMD cpu family 15h a unit mask was introduced for the Data Cache
Miss event (0x041/L1-dcache-load-misses). We need to enable bit 0
(first data cache miss or streaming store to a 64 B cache line) of
this mask to proper count data cache misses.

Now we set this bit for all families and models. In case a PMU does
not implement a unit mask for event 0x041 the bit is ignored.

Signed-off-by: Andre Przywara 
Signed-off-by: Robert Richter 
Signed-off-by: Peter Zijlstra 
Link: http://lkml.kernel.org/r/1302913676-14352-2-git-send-email-robert.richter@amd.com
Signed-off-by: Ingo Molnar

perf, x86: Add support for AMD family 15h core counters

2011-02-16T12:30:53+00:00

This patch adds support for AMD family 15h core counters. There are
major changes compared to family 10h. First, there is a new perfctr
msr range for up to 6 counters. Northbridge counters are separate
now. This patch only adds support for core counters. Second, certain
events may only be scheduled on certain counters. For this we need to
extend the event scheduling and constraints.

We use cpu feature flags to calculate family 15h msr address offsets.
This way we later can implement a faster ALTERNATIVE() version for
this.

Signed-off-by: Robert Richter 
Signed-off-by: Peter Zijlstra 
LKML-Reference: <20110215135210.GB5874@erda.amd.com>
Signed-off-by: Ingo Molnar