linux.git/arch/x86/kernel/cpu/mshyperv.c, branch v5.6

Merge branch 'linus' into x86/hyperv

2019-11-15T09:30:50+00:00

Pick up upstream fixes to avoid conflicts.

x86/hyperv: Allow guests to enable InvariantTSC

2019-11-12T10:44:21+00:00

If the hardware supports TSC scaling, Hyper-V will set bit 15 of the
HV_PARTITION_PRIVILEGE_MASK in guest VMs with a compatible Hyper-V
configuration version.  Bit 15 corresponds to the
AccessTscInvariantControls privilege.  If this privilege bit is set,
guests can access the HvSyntheticInvariantTscControl MSR: guests can
set bit 0 of this synthetic MSR to enable the InvariantTSC feature.
After setting the synthetic MSR, CPUID will enumerate support for
InvariantTSC.

Signed-off-by: Andrea Parri 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Michael Kelley 
Reviewed-by: Vitaly Kuznetsov 
Link: https://lkml.kernel.org/r/20191003155200.22022-1-parri.andrea@gmail.com

x86/hyperv: Set pv_info.name to "Hyper-V"

2019-10-18T11:33:38+00:00

Michael reported that the x86/hyperv initialization code prints the
following dmesg when running in a VM on Hyper-V:

  [    0.000738] Booting paravirtualized kernel on bare hardware

Let the x86/hyperv initialization code set pv_info.name to "Hyper-V" so
dmesg reports correctly:

  [    0.000172] Booting paravirtualized kernel on Hyper-V

[ tglx: Folded build fix provided by Yue ]

Reported-by: Michael Kelley 
Signed-off-by: Andrea Parri 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Wei Liu 
Reviewed-by: Michael Kelley 
Cc: YueHaibing 
Link: https://lkml.kernel.org/r/20191015103502.13156-1-parri.andrea@gmail.com

x86/hyperv: Hide pv_ops access for CONFIG_PARAVIRT=n

2019-08-28T10:25:06+00:00

hv_setup_sched_clock() references pv_ops which is only available when
CONFIG_PARAVIRT=Y.

Wrap it into a #ifdef

Signed-off-by: Tianyu Lan 
Signed-off-by: Thomas Gleixner 
Link: https://lkml.kernel.org/r/20190828080747.204419-1-Tianyu.Lan@microsoft.com

clocksource/drivers/hyperv: Add Hyper-V specific sched clock function

2019-08-23T14:59:54+00:00

Hyper-V guests use the default native_sched_clock() in
pv_ops.time.sched_clock on x86. But native_sched_clock() directly uses the
raw TSC value, which can be discontinuous in a Hyper-V VM.
    
Add the generic hv_setup_sched_clock() to set the sched clock function
appropriately. On x86, this sets pv_ops.time.sched_clock to read the
Hyper-V reference TSC value that is scaled and adjusted to be continuous.
    
Also move the Hyper-V reference TSC initialization much earlier in the boot
process so no discontinuity is observed when pv_ops.time.sched_clock
calculates its offset.

[ tglx: Folded build fix ]

Signed-off-by: Tianyu Lan 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Michael Kelley 
Link: https://lkml.kernel.org/r/20190814123216.32245-3-Tianyu.Lan@microsoft.com

Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2019-07-08T18:22:57+00:00

Pull x96 apic updates from Thomas Gleixner:
 "Updates for the x86 APIC interrupt handling and APIC timer:

   - Fix a long standing issue with spurious interrupts which was caused
     by the big vector management rework a few years ago. Robert Hodaszi
     provided finally enough debug data and an excellent initial failure
     analysis which allowed to understand the underlying issues.

     This contains a change to the core interrupt management code which
     is required to handle this correctly for the APIC/IO_APIC. The core
     changes are NOOPs for most architectures except ARM64. ARM64 is not
     impacted by the change as confirmed by Marc Zyngier.

   - Newer systems allow to disable the PIT clock for power saving
     causing panic in the timer interrupt delivery check of the IO/APIC
     when the HPET timer is not enabled either. While the clock could be
     turned on this would cause an endless whack a mole game to chase
     the proper register in each affected chipset.

     These systems provide the relevant frequencies for TSC, CPU and the
     local APIC timer via CPUID and/or MSRs, which allows to avoid the
     PIT/HPET based calibration. As the calibration code is the only
     usage of the legacy timers on modern systems and is skipped anyway
     when the frequencies are known already, there is no point in
     setting up the PIT and actually checking for the interrupt delivery
     via IO/APIC.

     To achieve this on a wide variety of platforms, the CPUID/MSR based
     frequency readout has been made more robust, which also allowed to
     remove quite some workarounds which turned out to be not longer
     required. Thanks to Daniel Drake for analysis, patches and
     verification"

* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/irq: Seperate unused system vectors from spurious entry again
  x86/irq: Handle spurious interrupt after shutdown gracefully
  x86/ioapic: Implement irq_get_irqchip_state() callback
  genirq: Add optional hardware synchronization for shutdown
  genirq: Fix misleading synchronize_irq() documentation
  genirq: Delay deactivation in free_irq()
  x86/timer: Skip PIT initialization on modern chipsets
  x86/apic: Use non-atomic operations when possible
  x86/apic: Make apic_bsp_setup() static
  x86/tsc: Set LAPIC timer period to crystal clock frequency
  x86/apic: Rename 'lapic_timer_frequency' to 'lapic_timer_period'
  x86/tsc: Use CPUID.0x16 to calculate missing crystal frequency

clocksource/drivers: Make Hyper-V clocksource ISA agnostic

2019-07-03T09:00:59+00:00

Hyper-V clock/timer code and data structures are currently mixed
in with other code in the ISA independent drivers/hv directory as
well as the ISA dependent Hyper-V code under arch/x86.

Consolidate this code and data structures into a Hyper-V clocksource driver
to better follow the Linux model. In doing so, separate out the ISA
dependent portions so the new clocksource driver works for x86 and for the
in-process Hyper-V on ARM64 code.

To start, move the existing clockevents code to create the new clocksource
driver. Update the VMbus driver to call initialization and cleanup routines
since the Hyper-V synthetic timers are not independently enumerated in
ACPI.

No behavior is changed and no new functionality is added.

Suggested-by: Marc Zyngier 
Signed-off-by: Michael Kelley 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Vitaly Kuznetsov 
Cc: "bp@alien8.de" 
Cc: "will.deacon@arm.com" 
Cc: "catalin.marinas@arm.com" 
Cc: "mark.rutland@arm.com" 
Cc: "linux-arm-kernel@lists.infradead.org" 
Cc: "gregkh@linuxfoundation.org" 
Cc: "linux-hyperv@vger.kernel.org" 
Cc: "olaf@aepfle.de" 
Cc: "apw@canonical.com" 
Cc: "jasowang@redhat.com" 
Cc: "marcelo.cerri@canonical.com" 
Cc: Sunil Muthuswamy 
Cc: KY Srinivasan 
Cc: "sashal@kernel.org" 
Cc: "vincenzo.frascino@arm.com" 
Cc: "linux-arch@vger.kernel.org" 
Cc: "linux-mips@vger.kernel.org" 
Cc: "linux-kselftest@vger.kernel.org" 
Cc: "arnd@arndb.de" 
Cc: "linux@armlinux.org.uk" 
Cc: "ralf@linux-mips.org" 
Cc: "paul.burton@mips.com" 
Cc: "daniel.lezcano@linaro.org" 
Cc: "salyzyn@android.com" 
Cc: "pcc@google.com" 
Cc: "shuah@kernel.org" 
Cc: "0x7f454c46@gmail.com" <0x7f454c46@gmail.com>
Cc: "linux@rasmusvillemoes.dk" 
Cc: "huw@codeweavers.com" 
Cc: "sfr@canb.auug.org.au" 
Cc: "pbonzini@redhat.com" 
Cc: "rkrcmar@redhat.com" 
Cc: "kvm@vger.kernel.org" 
Link: https://lkml.kernel.org/r/1561955054-1838-2-git-send-email-mikelley@microsoft.com

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441

2019-06-05T15:37:17+00:00

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation version 2 of the license

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 315 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Reviewed-by: Armijn Hemel 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.503150771@linutronix.de
Signed-off-by: Greg Kroah-Hartman

x86/apic: Rename 'lapic_timer_frequency' to 'lapic_timer_period'

2019-05-09T09:06:49+00:00

This variable is a period unit (number of clock cycles per jiffy),
not a frequency (which is number of cycles per second).

Give it a more appropriate name.

Suggested-by: Ingo Molnar 
Signed-off-by: Daniel Drake 
Reviewed-by: Thomas Gleixner 
Cc: Andy Lutomirski 
Cc: Borislav Petkov 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: len.brown@intel.com
Cc: linux@endlessm.com
Cc: rafael.j.wysocki@intel.com
Link: http://lkml.kernel.org/r/20190509055417.13152-2-drake@endlessm.com
Signed-off-by: Ingo Molnar

x86/Hyper-V: Set x2apic destination mode to physical when x2apic is available

2019-02-28T10:12:16+00:00

Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
set x2apic destination mode to physcial mode when x2apic is available
and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs have
8-bit APIC id.

Reviewed-by: Thomas Gleixner 
Reviewed-by: Michael Kelley 
Signed-off-by: Lan Tianyu 
Signed-off-by: Joerg Roedel