linux.git/arch/x86/kernel/cpu/mce, branch v6.14

x86/mce/amd: Remove shared threshold bank plumbing

2025-01-03T18:05:35+00:00

Legacy AMD systems include an integrated Northbridge that is represented
by MCA bank 4. This is the only non-core MCA bank in legacy systems. The
Northbridge is physically shared by all the CPUs within an AMD "Node".

However, in practice the "shared" MCA bank can only by managed by a
single CPU within that AMD Node. This is known as the "Node Base Core"
(NBC). For example, only the NBC will be able to read the MCA bank 4
registers; they will be Read-as-Zero for other CPUs. Also, the MCA
Thresholding interrupt will only signal the NBC; the other CPUs will not
receive it. This is enforced by hardware, and it should not be managed by
software.

The current AMD Thresholding code attempts to deal with the "shared" MCA
bank by micromanaging the bank's sysfs kobjects. However, this does not
follow the intended kobject use cases. It is also fragile, and it has
caused bugs in the past.

Modern AMD systems do not need this shared MCA bank support, and it
should not be needed on legacy systems either.

Remove the shared threshold bank code. Also, move the threshold struct
definitions to mce/amd.c, since they are no longer needed in amd_nb.c.

Signed-off-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Borislav Petkov (AMD) 
Link: https://lore.kernel.org/r/20241206161210.163701-2-yazen.ghannam@amd.com

x86/mce: Remove the redundant mce_hygon_feature_init()

2024-12-31T10:12:45+00:00

Get HYGON to directly call mce_amd_feature_init() and remove the redundant
mce_hygon_feature_init().

Suggested-by: Yazen Ghannam 
Signed-off-by: Qiuxu Zhuo 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Sohil Mehta 
Reviewed-by: Yazen Ghannam 
Link: https://lore.kernel.org/r/20241212140103.66964-7-qiuxu.zhuo@intel.com

x86/mce: Convert family/model mixed checks to VFM-based checks

2024-12-31T10:11:08+00:00

Convert family/model mixed checks to VFM-based checks to make the code
more compact. Simplify.

  [ bp: Drop the "what" from the commit message - it should be visible from
    the diff alone. ]

Suggested-by: Sohil Mehta 
Suggested-by: Dave Hansen 
Signed-off-by: Qiuxu Zhuo 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Tony Luck 
Reviewed-by: Sohil Mehta 
Reviewed-by: Yazen Ghannam 
Link: https://lore.kernel.org/r/20241212140103.66964-6-qiuxu.zhuo@intel.com

x86/mce: Break up __mcheck_cpu_apply_quirks()

2024-12-31T10:07:05+00:00

Split each vendor specific part into its own helper function.

Signed-off-by: Tony Luck 
Signed-off-by: Qiuxu Zhuo 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Sohil Mehta 
Reviewed-by: Yazen Ghannam 
Tested-by: Qiuxu Zhuo 
Link: https://lore.kernel.org/r/20241212140103.66964-5-qiuxu.zhuo@intel.com

x86/mce: Make four functions return bool

2024-12-30T21:06:36+00:00

Make those functions whose callers only care about success or failure return
a boolean value for better readability. Also, update the call sites
accordingly as the polarities of all the return values have been flipped.

No functional changes.

Suggested-by: Thomas Gleixner 
Signed-off-by: Qiuxu Zhuo 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Sohil Mehta 
Reviewed-by: Yazen Ghannam 
Link: https://lore.kernel.org/r/20241212140103.66964-4-qiuxu.zhuo@intel.com

x86/mce/threshold: Remove the redundant this_cpu_dec_return()

2024-12-30T18:45:03+00:00

The 'storm' variable points to this_cpu_ptr(&storm_desc). Access the
'stormy_bank_count' field through the 'storm' to avoid calling
this_cpu_*() on the same per-CPU variable twice.

This minor optimization reduces the text size by 16 bytes.

  $ size threshold.o.*
     text	   data	    bss	    dec	    hex	filename
     1395	   1664	      0	   3059	    bf3	threshold.o.old
     1379	   1664	      0	   3043	    be3	threshold.o.new

No functional changes intended.

Signed-off-by: Qiuxu Zhuo 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Tony Luck 
Reviewed-by: Nikolay Borisov 
Reviewed-by: Sohil Mehta 
Reviewed-by: Yazen Ghannam 
Link: https://lore.kernel.org/r/20241212140103.66964-3-qiuxu.zhuo@intel.com

x86/mce: Make several functions return bool

2024-12-30T18:05:50+00:00

Make several functions that return 0 or 1 return a boolean value for
better readability.

No functional changes are intended.

Signed-off-by: Qiuxu Zhuo 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Tony Luck 
Reviewed-by: Nikolay Borisov 
Reviewed-by: Sohil Mehta 
Reviewed-by: Yazen Ghannam 
Link: https://lore.kernel.org/r/20241212140103.66964-2-qiuxu.zhuo@intel.com

x86/mce/apei: Handle variable SMCA BERT record size

2024-10-31T09:45:59+00:00

The ACPI Boot Error Record Table (BERT) is being used by the kernel to report
errors that occurred in a previous boot. On some modern AMD systems, these
very errors within the BERT are reported through the x86 Common Platform Error
Record (CPER) format which consists of one or more Processor Context
Information Structures.

These context structures provide a starting address and represent an x86 MSR
range in which the data constitutes a contiguous set of MSRs starting from,
and including the starting address.

It's common, for AMD systems that implement this behavior, that the MSR range
represents the MCAX register space used for the Scalable MCA feature. The
apei_smca_report_x86_error() function decodes and passes this information
through the MCE notifier chain. However, this function assumes a fixed
register size based on the original HW/FW implementation.

This assumption breaks with the addition of two new MCAX registers viz.
MCA_SYND1 and MCA_SYND2. These registers are added at the end of the MCAX
register space, so they won't be included when decoding the CPER data.

Rework apei_smca_report_x86_error() to support a variable register array size.
This covers any case where the MSR context information starts at the MCAX
address for MCA_STATUS and ends at any other register within the MCAX register
space.

  [ Yazen: Add Avadhut as co-developer for wrapper changes.]
  [ bp: Massage. ]

Signed-off-by: Yazen Ghannam 
Co-developed-by: Avadhut Naik 
Signed-off-by: Avadhut Naik 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Qiuxu Zhuo 
Link: https://lore.kernel.org/r/20241022194158.110073-5-avadhut.naik@amd.com

x86/MCE/AMD: Add support for new MCA_SYND{1,2} registers

2024-10-31T09:36:07+00:00

Starting with Zen4, AMD's Scalable MCA systems incorporate two new registers:
MCA_SYND1 and MCA_SYND2.

These registers will include supplemental error information in addition to the
existing MCA_SYND register. The data within these registers is considered
valid if MCA_STATUS[SyndV] is set.

Userspace error decoding tools like rasdaemon gather related hardware error
information through the tracepoints.

Therefore, export these two registers through the mce_record tracepoint so
that tools like rasdaemon can parse them and output the supplemental error
information like FRU text contained in them.

  [ bp: Massage. ]

Signed-off-by: Yazen Ghannam 
Signed-off-by: Avadhut Naik 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Qiuxu Zhuo 
Link: https://lore.kernel.org/r/20241022194158.110073-4-avadhut.naik@amd.com

x86/mce: Add wrapper for struct mce to export vendor specific info

2024-10-30T16:18:59+00:00

Currently, exporting new additional machine check error information
involves adding new fields for the same at the end of the struct mce.
This additional information can then be consumed through mcelog or
tracepoint.

However, as new MSRs are being added (and will be added in the future)
by CPU vendors on their newer CPUs with additional machine check error
information to be exported, the size of struct mce will balloon on some
CPUs, unnecessarily, since those fields are vendor-specific. Moreover,
different CPU vendors may export the additional information in varying
sizes.

The problem particularly intensifies since struct mce is exposed to
userspace as part of UAPI. It's bloating through vendor-specific data
should be avoided to limit the information being sent out to userspace.

Add a new structure mce_hw_err to wrap the existing struct mce. The same
will prevent its ballooning since vendor-specifc data, if any, can now be
exported through a union within the wrapper structure and through
__dynamic_array in mce_record tracepoint.

Furthermore, new internal kernel fields can be added to the wrapper
struct without impacting the user space API.

  [ bp: Restore reverse x-mas tree order of function vars declarations. ]

Suggested-by: Borislav Petkov (AMD) 
Signed-off-by: Avadhut Naik 
Signed-off-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Qiuxu Zhuo 
Link: https://lore.kernel.org/r/20241022194158.110073-2-avadhut.naik@amd.com