linux.git/arch/x86/kernel/cpu/bugs.c, branch v4.18

x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR

2018-07-03T07:45:48+00:00

On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the
SSBD mitigation support should use the SPEC_CTRL MSR. Other features could
have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD
mitigation option is in place.

Update the SSBD support to check for the actual SSBD features that will
use the SPEC_CTRL MSR.

Signed-off-by: Tom Lendacky 
Cc: Borislav Petkov 
Cc: David Woodhouse 
Cc: Konrad Rzeszutek Wilk 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage")
Link: http://lkml.kernel.org/r/20180702213602.29202.33151.stgit@tlendack-t1.amdoffice.net
Signed-off-by: Ingo Molnar

x86/pti: Don't report XenPV as vulnerable

2018-06-21T12:14:52+00:00

Xen PV domain kernel is not by design affected by meltdown as it's
enforcing split CR3 itself. Let's not report such systems as "Vulnerable"
in sysfs (we're also already forcing PTI to off in X86_HYPER_XEN_PV cases);
the security of the system ultimately depends on presence of mitigation in
the Hypervisor, which can't be easily detected from DomU; let's report
that.

Reported-and-tested-by: Mike Latimer 
Signed-off-by: Jiri Kosina 
Signed-off-by: Thomas Gleixner 
Acked-by: Juergen Gross 
Cc: Borislav Petkov 
Link: https://lkml.kernel.org/r/nycvar.YFH.7.76.1806180959080.6203@cbobk.fhfr.pm
[ Merge the user-visible string into a single line. ]
Signed-off-by: Ingo Molnar

x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features

2018-06-06T12:13:17+00:00

Both AMD and Intel can have SPEC_CTRL_MSR for SSBD.

However AMD also has two more other ways of doing it - which
are !SPEC_CTRL MSR ways.

Signed-off-by: Konrad Rzeszutek Wilk 
Signed-off-by: Thomas Gleixner 
Cc: Kees Cook 
Cc: kvm@vger.kernel.org
Cc: KarimAllah Ahmed 
Cc: andrew.cooper3@citrix.com
Cc: "H. Peter Anvin" 
Cc: Borislav Petkov 
Cc: David Woodhouse 
Link: https://lkml.kernel.org/r/20180601145921.9500-4-konrad.wilk@oracle.com

x86/bugs: Add AMD's SPEC_CTRL MSR usage

2018-06-06T12:13:16+00:00

The AMD document outlining the SSBD handling
124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
mentions that if CPUID 8000_0008.EBX[24] is set we should be using
the SPEC_CTRL MSR (0x48) over the VIRT SPEC_CTRL MSR (0xC001_011f)
for speculative store bypass disable.

This in effect means we should clear the X86_FEATURE_VIRT_SSBD
flag so that we would prefer the SPEC_CTRL MSR.

See the document titled:
   124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

A copy of this document is available at
   https://bugzilla.kernel.org/show_bug.cgi?id=199889

Signed-off-by: Konrad Rzeszutek Wilk 
Signed-off-by: Thomas Gleixner 
Cc: Tom Lendacky 
Cc: Janakarajan Natarajan 
Cc: kvm@vger.kernel.org
Cc: KarimAllah Ahmed 
Cc: andrew.cooper3@citrix.com
Cc: Joerg Roedel 
Cc: Radim Krčmář 
Cc: Andy Lutomirski 
Cc: "H. Peter Anvin" 
Cc: Paolo Bonzini 
Cc: Borislav Petkov 
Cc: David Woodhouse 
Cc: Kees Cook 
Link: https://lkml.kernel.org/r/20180601145921.9500-3-konrad.wilk@oracle.com

x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFG

2018-05-17T15:09:21+00:00

Add the necessary logic for supporting the emulated VIRT_SPEC_CTRL MSR to
x86_virt_spec_ctrl().  If either X86_FEATURE_LS_CFG_SSBD or
X86_FEATURE_VIRT_SPEC_CTRL is set then use the new guest_virt_spec_ctrl
argument to check whether the state must be modified on the host. The
update reuses speculative_store_bypass_update() so the ZEN-specific sibling
coordination can be reused.

Signed-off-by: Thomas Gleixner

x86/bugs: Rework spec_ctrl base and mask logic

2018-05-17T15:09:20+00:00

x86_spec_ctrL_mask is intended to mask out bits from a MSR_SPEC_CTRL value
which are not to be modified. However the implementation is not really used
and the bitmask was inverted to make a check easier, which was removed in
"x86/bugs: Remove x86_spec_ctrl_set()"

Aside of that it is missing the STIBP bit if it is supported by the
platform, so if the mask would be used in x86_virt_spec_ctrl() then it
would prevent a guest from setting STIBP.

Add the STIBP bit if supported and use the mask in x86_virt_spec_ctrl() to
sanitize the value which is supplied by the guest.

Signed-off-by: Thomas Gleixner 
Reviewed-by: Borislav Petkov

x86/bugs: Remove x86_spec_ctrl_set()

2018-05-17T15:09:20+00:00

x86_spec_ctrl_set() is only used in bugs.c and the extra mask checks there
provide no real value as both call sites can just write x86_spec_ctrl_base
to MSR_SPEC_CTRL. x86_spec_ctrl_base is valid and does not need any extra
masking or checking.

Signed-off-by: Thomas Gleixner 
Reviewed-by: Borislav Petkov 
Reviewed-by: Konrad Rzeszutek Wilk

x86/bugs: Expose x86_spec_ctrl_base directly

2018-05-17T15:09:19+00:00

x86_spec_ctrl_base is the system wide default value for the SPEC_CTRL MSR.
x86_spec_ctrl_get_default() returns x86_spec_ctrl_base and was intended to
prevent modification to that variable. Though the variable is read only
after init and globaly visible already.

Remove the function and export the variable instead.

Signed-off-by: Thomas Gleixner 
Reviewed-by: Borislav Petkov 
Reviewed-by: Konrad Rzeszutek Wilk

x86/bugs: Unify x86_spec_ctrl_{set_guest,restore_host}

2018-05-17T15:09:19+00:00

Function bodies are very similar and are going to grow more almost
identical code. Add a bool arg to determine whether SPEC_CTRL is being set
for the guest or restored to the host.

No functional changes.

Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Konrad Rzeszutek Wilk

x86/speculation: Rework speculative_store_bypass_update()

2018-05-17T15:09:19+00:00

The upcoming support for the virtual SPEC_CTRL MSR on AMD needs to reuse
speculative_store_bypass_update() to avoid code duplication. Add an
argument for supplying a thread info (TIF) value and create a wrapper
speculative_store_bypass_update_current() which is used at the existing
call site.

Signed-off-by: Thomas Gleixner 
Reviewed-by: Borislav Petkov 
Reviewed-by: Konrad Rzeszutek Wilk