linux.git/arch/x86/kernel/cpu/amd.c, branch v2.6.28

x86: print out apic id in hex format

2008-10-16T14:53:09+00:00

Signed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86: make amd.c have 64bit support code

2008-09-08T13:32:02+00:00

Signed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86: merge header in amd_64.c

2008-09-08T13:32:01+00:00

Singed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86: cpu make amd.c more like amd_64.c v2

2008-09-08T13:31:58+00:00

1. make 32bit have early_init_amd_mc and amd_detect_cmp
2. seperate init_amd_k5/k6/k7 ...

v2: fix compiling for !CONFIG_SMP

Signed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86, cpu init: call early_init_xxx in init_xxx

2008-09-06T12:09:14+00:00

so we:

 1. could set some cap to ap
 2. restore some cap after memset in identify_cpu for boot cpu

esp for CONSTANT_TSC this matters, as:

before this patch:
 flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow rep_good nopl pni monitor cx16 lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs

after this patch:
 flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nopl pni monitor cx16 lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs

so constant_tsc is back...

Signed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86: remove duplicated get_model_name() calling

2008-09-06T12:09:12+00:00

Signed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86: remove cpu_vendor_dev

2008-09-04T19:09:45+00:00

1. add c_x86_vendor into cpu_dev
2. change cpu_devs to static
3. check c_x86_vendor before put that cpu_dev into array
4. remove alignment for 64bit
5. order the sequence in cpu_devs according to link sequence...
   so could put intel at first, then amd...

Signed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86: move mtrr cpu cap setting early in early_init_xxxx

2008-09-04T19:09:43+00:00

Krzysztof Helt found MTRR is not detected on k6-2

root cause:
	we moved mtrr_bp_init() early for mtrr trimming,
and in early_detect we only read the CPU capability from cpuid,
so some cpu doesn't have that bit in cpuid.

So we need to add early_init_xxxx to preset those bit before mtrr_bp_init
for those earlier cpus.

this patch is for v2.6.27

Reported-by: Krzysztof Helt 
Signed-off-by: Yinghai Lu 
Signed-off-by: Ingo Molnar

x86: reduce force_mwait visibility

2008-07-18T22:55:09+00:00

It's not used anywhere outside its single referencing file.

Signed-off-by: Jan Beulich 
Signed-off-by: H. Peter Anvin

x86: Move PCI IO ECS code to x86/pci

2008-07-08T05:47:39+00:00

"Form follows function". Code is now where it belongs to.

Signed-off-by: Robert Richter 
Signed-off-by: Ingo Molnar