linux.git/arch/x86/entry, branch v6.16

x86/bugs: Rename MDS machinery to something more generic

2025-06-16T16:45:18+00:00

It will be used by other x86 mitigations.

No functional changes.

Signed-off-by: Borislav Petkov (AMD) 
Reviewed-by: Pawan Gupta

Merge tag 'x86-entry-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2025-05-27T04:21:12+00:00

Pull x86 vdso updates from Ingo Molnar:
 "Two changes to simplify the x86 vDSO code a bit"

* tag 'x86-entry-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/vdso: Remove redundant #ifdeffery around in_ia32_syscall()
  x86/vdso: Remove #ifdeffery around page setup variants

x86/mm/64: Make 5-level paging support unconditional

2025-05-17T08:38:16+00:00

Both Intel and AMD CPUs support 5-level paging, which is expected to
become more widely adopted in the future. All major x86 Linux
distributions have the feature enabled.

Remove CONFIG_X86_5LEVEL and related #ifdeffery for it to make it more readable.

Suggested-by: Borislav Petkov 
Signed-off-by: Kirill A. Shutemov 
Signed-off-by: Ingo Molnar 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Borislav Petkov (AMD) 
Cc: Dave Hansen 
Cc: H. Peter Anvin 
Cc: Linus Torvalds 
Link: https://lore.kernel.org/r/20250516123306.3812286-4-kirill.shutemov@linux.intel.com

x86/its: Align RETs in BHB clear sequence to avoid thunking

2025-05-09T20:22:05+00:00

The software mitigation for BHI is to execute BHB clear sequence at syscall
entry, and possibly after a cBPF program. ITS mitigation thunks RETs in the
lower half of the cacheline. This causes the RETs in the BHB clear sequence
to be thunked as well, adding unnecessary branches to the BHB clear
sequence.

Since the sequence is in hot path, align the RET instructions in the
sequence to avoid thunking.

This is how disassembly clear_bhb_loop() looks like after this change:

   0x44 <+4>:     mov    $0x5,%ecx
   0x49 <+9>:     call   0xffffffff81001d9b 
   0x4e <+14>:    jmp    0xffffffff81001de5 
   0x53 <+19>:    int3
   ...
   0x9b <+91>:    call   0xffffffff81001dce 
   0xa0 <+96>:    ret
   0xa1 <+97>:    int3
   ...
   0xce <+142>:   mov    $0x5,%eax
   0xd3 <+147>:   jmp    0xffffffff81001dd6 
   0xd5 <+149>:   nop
   0xd6 <+150>:   sub    $0x1,%eax
   0xd9 <+153>:   jne    0xffffffff81001dd3 
   0xdb <+155>:   sub    $0x1,%ecx
   0xde <+158>:   jne    0xffffffff81001d9b 
   0xe0 <+160>:   ret
   0xe1 <+161>:   int3
   0xe2 <+162>:   int3
   0xe3 <+163>:   int3
   0xe4 <+164>:   int3
   0xe5 <+165>:   lfence
   0xe8 <+168>:   pop    %rbp
   0xe9 <+169>:   ret

Suggested-by: Andrew Cooper 
Signed-off-by: Pawan Gupta 
Signed-off-by: Dave Hansen 
Reviewed-by: Alexandre Chartre

x86/vdso: Remove redundant #ifdeffery around in_ia32_syscall()

2025-04-22T12:24:07+00:00

The #ifdefs only guard code that is also guarded by in_ia32_syscall(),
which already contains the same #ifdef itself.

Signed-off-by: Thomas Weißschuh 
Signed-off-by: Ingo Molnar 
Cc: Andrew Cooper 
Cc: Andy Lutomirski 
Cc: Brian Gerst 
Cc: Eric Biederman 
Cc: H. Peter Anvin 
Cc: Juergen Gross 
Cc: Kees Cook 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Rik van Riel 
Link: https://lore.kernel.org/r/20240910-x86-vdso-ifdef-v1-2-877c9df9b081@linutronix.de

x86/vdso: Remove #ifdeffery around page setup variants

2025-04-22T12:24:07+00:00

Replace the open-coded ifdefs in C sources files with IS_ENABLED().
This makes the code easier to read and enables the compiler to typecheck
also the disabled parts, before optimizing them away.
To make this work, also remove the ifdefs from declarations of used
variables.

Signed-off-by: Thomas Weißschuh 
Signed-off-by: Ingo Molnar 
Cc: Andrew Cooper 
Cc: Andy Lutomirski 
Cc: Brian Gerst 
Cc: Eric Biederman 
Cc: H. Peter Anvin 
Cc: Juergen Gross 
Cc: Kees Cook 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Rik van Riel 
Link: https://lore.kernel.org/r/20240910-x86-vdso-ifdef-v1-1-877c9df9b081@linutronix.de

x86/bugs: Use SBPB in write_ibpb() if applicable

2025-04-09T10:41:30+00:00

write_ibpb() does IBPB, which (among other things) flushes branch type
predictions on AMD.  If the CPU has SRSO_NO, or if the SRSO mitigation
has been disabled, branch type flushing isn't needed, in which case the
lighter-weight SBPB can be used.

The 'x86_pred_cmd' variable already keeps track of whether IBPB or SBPB
should be used.  Use that instead of hardcoding IBPB.

Signed-off-by: Josh Poimboeuf 
Signed-off-by: Ingo Molnar 
Link: https://lore.kernel.org/r/17c5dcd14b29199b75199d67ff7758de9d9a4928.1744148254.git.jpoimboe@kernel.org

x86/bugs: Rename entry_ibpb() to write_ibpb()

2025-04-09T10:41:29+00:00

There's nothing entry-specific about entry_ibpb().  In preparation for
calling it from elsewhere, rename it to write_ibpb().

Signed-off-by: Josh Poimboeuf 
Signed-off-by: Ingo Molnar 
Link: https://lore.kernel.org/r/1e54ace131e79b760de3fe828264e26d0896e3ac.1744148254.git.jpoimboe@kernel.org

mseal sysmap: enable x86-64

2025-04-01T22:17:15+00:00

Provide support for CONFIG_MSEAL_SYSTEM_MAPPINGS on x86-64, covering the
vdso, vvar, vvar_vclock.

Production release testing passes on Android and Chrome OS.

Link: https://lkml.kernel.org/r/20250305021711.3867874-4-jeffxu@google.com
Signed-off-by: Jeff Xu 
Reviewed-by: Lorenzo Stoakes 
Reviewed-by: Liam R. Howlett 
Reviewed-by: Kees Cook 
Cc: Adhemerval Zanella 
Cc: Alexander Mikhalitsyn 
Cc: Alexey Dobriyan 
Cc: Andrei Vagin 
Cc: Anna-Maria Behnsen 
Cc: Ard Biesheuvel 
Cc: Benjamin Berg 
Cc: Christoph Hellwig 
Cc: Dave Hansen 
Cc: David Rientjes 
Cc: David S. Miller 
Cc: Elliot Hughes 
Cc: Florian Faineli 
Cc: Greg Ungerer 
Cc: Guenter Roeck 
Cc: Heiko Carstens 
Cc: Helge Deller 
Cc: Hyeonggon Yoo <42.hyeyoo@gmail.com>
Cc: Ingo Molnar 
Cc: Jann Horn 
Cc: Jason A. Donenfeld 
Cc: Johannes Berg 
Cc: Jorge Lucangeli Obes 
Cc: Linus Waleij 
Cc: Mark Rutland 
Cc: Matthew Wilcow (Oracle) 
Cc: Michael Ellerman 
Cc: Michal Hocko 
Cc: Miguel Ojeda 
Cc: Mike Rapoport 
Cc: Oleg Nesterov 
Cc: Pedro Falcato 
Cc: Peter Xu 
Cc: Randy Dunlap 
Cc: Stephen Röttger 
Cc: Thomas Weißschuh 
Cc: Vlastimil Babka 
Signed-off-by: Andrew Morton

Merge tag 'x86-urgent-2025-03-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2025-03-30T22:25:15+00:00

Pull misc x86 fixes and updates from Ingo Molnar:

 - Fix a large number of x86 Kconfig dependency and help text accuracy
   bugs/problems, by Mateusz Jończyk and David Heideberg

 - Fix a VM_PAT interaction with fork() crash. This also touches core
   kernel code

 - Fix an ORC unwinder bug for interrupt entries

 - Fixes and cleanups

 - Fix an AMD microcode loader bug that can promote verification
   failures into success

 - Add early-printk support for MMIO based UARTs on an x86 board that
   had no other serial debugging facility and also experienced early
   boot crashes

* tag 'x86-urgent-2025-03-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/microcode/AMD: Fix __apply_microcode_amd()'s return value
  x86/mm/pat: Fix VM_PAT handling when fork() fails in copy_page_range()
  x86/fpu: Update the outdated comment above fpstate_init_user()
  x86/early_printk: Add support for MMIO-based UARTs
  x86/dumpstack: Fix inaccurate unwinding from exception stacks due to misplaced assignment
  x86/entry: Fix ORC unwinder for PUSH_REGS with save_ret=1
  x86/Kconfig: Fix lists in X86_EXTENDED_PLATFORM help text
  x86/Kconfig: Correct X86_X2APIC help text
  x86/speculation: Remove the extra #ifdef around CALL_NOSPEC
  x86/Kconfig: Document release year of glibc 2.3.3
  x86/Kconfig: Make CONFIG_PCI_CNB20LE_QUIRK depend on X86_32
  x86/Kconfig: Document CONFIG_PCI_MMCONFIG
  x86/Kconfig: Update lists in X86_EXTENDED_PLATFORM
  x86/Kconfig: Move all X86_EXTENDED_PLATFORM options together
  x86/Kconfig: Always enable ARCH_SPARSEMEM_ENABLE
  x86/Kconfig: Enable X86_X2APIC by default and improve help text