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<title>linux.git/arch/unicore32/include/asm/cacheflush.h, branch v4.16</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>unicore32: make dma_cache_sync a no-op</title>
<updated>2017-10-19T14:37:36+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2017-08-27T08:22:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a535bb801036268c3d057d7584e9c8f35f69aad4'/>
<id>a535bb801036268c3d057d7584e9c8f35f69aad4</id>
<content type='text'>
unicore32 does not implement DMA_ATTR_NON_CONSISTENT allocations, so it
doesn't make any sense to do any work in dma_cache_sync given that it
must be a no-op when dma_alloc_attrs returns coherent memory.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
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<pre>
unicore32 does not implement DMA_ATTR_NON_CONSISTENT allocations, so it
doesn't make any sense to do any work in dma_cache_sync given that it
must be a no-op when dma_alloc_attrs returns coherent memory.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>unicore32 core architecture: mm related: consistent device DMA handling</title>
<updated>2011-03-17T01:19:09+00:00</updated>
<author>
<name>GuanXuetao</name>
<email>gxt@mprc.pku.edu.cn</email>
</author>
<published>2011-01-15T10:18:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=10c9c10c31514564b09c153432a42ffaea3ce831'/>
<id>10c9c10c31514564b09c153432a42ffaea3ce831</id>
<content type='text'>
This patch implements consistent device DMA handling of memory management.
DMA device operations are also here.

Signed-off-by: Guan Xuetao &lt;gxt@mprc.pku.edu.cn&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
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<pre>
This patch implements consistent device DMA handling of memory management.
DMA device operations are also here.

Signed-off-by: Guan Xuetao &lt;gxt@mprc.pku.edu.cn&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</pre>
</div>
</content>
</entry>
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