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<title>linux.git/arch/sh, branch v2.6.28</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>sh: Disable GENERIC_HARDIRQS_NO__DO_IRQ for unconverted platforms.</title>
<updated>2008-12-16T07:42:53+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2008-12-08T02:45:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f9d62c009637f9581cdd7f6e430f8eec511c8587'/>
<id>f9d62c009637f9581cdd7f6e430f8eec511c8587</id>
<content type='text'>
Presently limited to Cayman, Dreamcast, Microdev, and SystemH 7751.
Re-enable it for everyone once these have been fixed up.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
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<pre>
Presently limited to Cayman, Dreamcast, Microdev, and SystemH 7751.
Re-enable it for everyone once these have been fixed up.

Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>serial: sh-sci: Reorder the SCxTDR write after the TDxE clear.</title>
<updated>2008-11-13T08:46:06+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2008-11-13T08:46:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=272966c070237c8cb540fe67e06df51bc6ea9cc2'/>
<id>272966c070237c8cb540fe67e06df51bc6ea9cc2</id>
<content type='text'>
Under qemu there is a race between the TDxE read-and-clear and the SCxTDR
write. While on hardware it can be gauranteed that the read-and-clear
will happen prior to the character being written out, no such assumption
can be made under emulation. As this path happens with IRQs off and the
hardware itself doesn't care about the ordering, move the SCxTDR write
until after the read-and-clear.

Signed-off-by: Vladimir Prus &lt;vladimir@codesourcery.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
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<pre>
Under qemu there is a race between the TDxE read-and-clear and the SCxTDR
write. While on hardware it can be gauranteed that the read-and-clear
will happen prior to the character being written out, no such assumption
can be made under emulation. As this path happens with IRQs off and the
hardware itself doesn't care about the ordering, move the SCxTDR write
until after the read-and-clear.

Signed-off-by: Vladimir Prus &lt;vladimir@codesourcery.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: __copy_user function can corrupt the stack in case of exception</title>
<updated>2008-11-13T08:40:30+00:00</updated>
<author>
<name>Stuart MENEFY</name>
<email>stuart.menefy@st.com</email>
</author>
<published>2008-10-10T18:49:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5d52013cbb3d39bde9f5a6023193058eeb112e98'/>
<id>5d52013cbb3d39bde9f5a6023193058eeb112e98</id>
<content type='text'>
The __copy_user function can corrupt the stack in the case of a
non-trivial length of data, and either of the first two move instructions
cause an exception. This is because the fixup for these two instructions
is mapped to the no_pop case, but these instructions execute after the
stack is pushed.

This change creates an explicit NO_POP exception mapping macro, and uses
it for the two instructions executed in the trivial case where no stack
pushes occur.

More information at ST Linux bugzilla:

	https://bugzilla.stlinux.com/show_bug.cgi?id=4824

Signed-off-by: Dylan Reid &lt;dylan_reid@bose.com&gt;
Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
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<pre>
The __copy_user function can corrupt the stack in the case of a
non-trivial length of data, and either of the first two move instructions
cause an exception. This is because the fixup for these two instructions
is mapped to the no_pop case, but these instructions execute after the
stack is pushed.

This change creates an explicit NO_POP exception mapping macro, and uses
it for the two instructions executed in the trivial case where no stack
pushes occur.

More information at ST Linux bugzilla:

	https://bugzilla.stlinux.com/show_bug.cgi?id=4824

Signed-off-by: Dylan Reid &lt;dylan_reid@bose.com&gt;
Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Fixed the TMU0 reload value on resume</title>
<updated>2008-11-13T08:40:30+00:00</updated>
<author>
<name>Francesco VIRLINZI</name>
<email>francesco.virlinzi@st.com</email>
</author>
<published>2008-10-15T09:58:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2cd0ebc83d771220eeddec91fd6d4cfefc2cc46e'/>
<id>2cd0ebc83d771220eeddec91fd6d4cfefc2cc46e</id>
<content type='text'>
This patch fixes the TMU0 interrupt frequency on suspend/resume.
During the resume the kernel reprograms the TMU0.ClockEvent mode
but if the mode is periodic than the TMU0.TCOR is updated with
a random wrong value without taking care latest valid saved value.

There was no problem with No_HZ system where TMU0.TCOR isn't used.

Signed-off-by: Francesco M. Virlinzi &lt;francesco.virlinzi@st.com&gt;
Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
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<pre>
This patch fixes the TMU0 interrupt frequency on suspend/resume.
During the resume the kernel reprograms the TMU0.ClockEvent mode
but if the mode is periodic than the TMU0.TCOR is updated with
a random wrong value without taking care latest valid saved value.

There was no problem with No_HZ system where TMU0.TCOR isn't used.

Signed-off-by: Francesco M. Virlinzi &lt;francesco.virlinzi@st.com&gt;
Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Don't factor in PAGE_OFFSET for valid_phys_addr_range() check.</title>
<updated>2008-11-13T06:38:02+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2008-11-13T06:38:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=10840f034e2329150ce0e683e636ea13b268d333'/>
<id>10840f034e2329150ce0e683e636ea13b268d333</id>
<content type='text'>
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: early printk port type fix</title>
<updated>2008-11-13T06:37:07+00:00</updated>
<author>
<name>Magnus Damm</name>
<email>damm@igel.co.jp</email>
</author>
<published>2008-11-13T06:33:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=bfbedf787c6b77270679429caadb044b2d33c94c'/>
<id>bfbedf787c6b77270679429caadb044b2d33c94c</id>
<content type='text'>
Add PORT_SCIF to unbreak the early printk code.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add PORT_SCIF to unbreak the early printk code.

Signed-off-by: Magnus Damm &lt;damm@igel.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Provide a sane valid_phys_addr_range() to prevent TLB reset with PMB.</title>
<updated>2008-11-12T03:53:48+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2008-11-12T03:53:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=185aed75570fb4f78ef283dfa26cd9da5fa06a91'/>
<id>185aed75570fb4f78ef283dfa26cd9da5fa06a91</id>
<content type='text'>
With the PMB enabled, only P1SEG and up are covered by the PMB mappings,
meaning that situations where out-of-bounds physical addresses are read
from will lead to TLB reset after the PMB miss, allowing for use cases
like dd if=/dev/mem to reset the TLB.

Fix this up to make sure the reference is between __MEMORY_START (phys)
and __pa(high_memory). This is coherent across all variants of sh/sh64
with and without MMU, though the PMB bug itself is only applicable to
SH-4A parts.

Reported-by: Hideo Saito &lt;saito@densan.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
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<pre>
With the PMB enabled, only P1SEG and up are covered by the PMB mappings,
meaning that situations where out-of-bounds physical addresses are read
from will lead to TLB reset after the PMB miss, allowing for use cases
like dd if=/dev/mem to reset the TLB.

Fix this up to make sure the reference is between __MEMORY_START (phys)
and __pa(high_memory). This is coherent across all variants of sh/sh64
with and without MMU, though the PMB bug itself is only applicable to
SH-4A parts.

Reported-by: Hideo Saito &lt;saito@densan.co.jp&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fix sci type for SH7723</title>
<updated>2008-11-12T03:29:56+00:00</updated>
<author>
<name>Yoshihiro Shimoda</name>
<email>shimoda.yoshihiro@renesas.com</email>
</author>
<published>2008-11-11T03:19:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=51ee3d92bfb983790b9ed576c22f59d42adff329'/>
<id>51ee3d92bfb983790b9ed576c22f59d42adff329</id>
<content type='text'>
This patch changes sci type of SH7723 from PORT_SCI to PORT_SCIFA.

Signed-off-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch changes sci type of SH7723 from PORT_SCI to PORT_SCIFA.

Signed-off-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: Handle fixmap TLB eviction more coherently.</title>
<updated>2008-11-10T11:00:45+00:00</updated>
<author>
<name>Paul Mundt</name>
<email>lethal@linux-sh.org</email>
</author>
<published>2008-11-10T11:00:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=acca4f4d9bd657e8bc7e1665ba5077465138f133'/>
<id>acca4f4d9bd657e8bc7e1665ba5077465138f133</id>
<content type='text'>
There was a race in the kmap_coherent() implementation. While we
guarded against preemption, there was nothing preventing eviction of
the pre-faulted fixmap entry from the UTLB. Under certain workloads
this would result in the fixmap entries used for cache colouring being
evicted from the UTLB in the midst of a copy_page().

In addition to pre-faulting, we also make sure to preserve the PTEs
in the kernel page table and introduce a cached PTE for kmap_coherent()
usage. This follows a similar change on MIPS ("[MIPS] Fix aliasing bug
in copy_to_user_page / copy_from_user_page").

Reported-by: Hideo Saito &lt;saito@densan.co.jp&gt;
Reported-by: CHIKAMA Masaki &lt;masaki.chikama@gmail.com&gt;
Tested-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There was a race in the kmap_coherent() implementation. While we
guarded against preemption, there was nothing preventing eviction of
the pre-faulted fixmap entry from the UTLB. Under certain workloads
this would result in the fixmap entries used for cache colouring being
evicted from the UTLB in the midst of a copy_page().

In addition to pre-faulting, we also make sure to preserve the PTEs
in the kernel page table and introduce a cached PTE for kmap_coherent()
usage. This follows a similar change on MIPS ("[MIPS] Fix aliasing bug
in copy_to_user_page / copy_from_user_page").

Reported-by: Hideo Saito &lt;saito@densan.co.jp&gt;
Reported-by: CHIKAMA Masaki &lt;masaki.chikama@gmail.com&gt;
Tested-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sh: fix sh2a cache entry_mask</title>
<updated>2008-10-31T07:29:20+00:00</updated>
<author>
<name>Yoshihiro Shimoda</name>
<email>shimoda.yoshihiro@renesas.com</email>
</author>
<published>2008-08-07T04:54:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=216813a8bb4db97eb7a6e75c533894430053df48'/>
<id>216813a8bb4db97eb7a6e75c533894430053df48</id>
<content type='text'>
fix sh2a cache entry_mask in __flush_{purge,invalidate}_region.

Signed-off-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
fix sh2a cache entry_mask in __flush_{purge,invalidate}_region.

Signed-off-by: Yoshihiro Shimoda &lt;shimoda.yoshihiro@renesas.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</pre>
</div>
</content>
</entry>
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