linux.git/arch/sh/kernel/setup.c, branch v2.6.30 Linux kernel source tree sh: Fix up -Wformat-security whining. 2009-03-30T23:25:54+00:00 Paul Mundt lethal@linux-sh.org 2009-03-30T23:25:54+00:00 0bd4781d40ffc3bff939a2540041144b99c373b8 Triggers -Werror on gcc-4.3: arch/sh/kernel/setup.c: In function 'early_parse_mem': arch/sh/kernel/setup.c:111: error: format not a string literal and no format arguments ... Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Triggers -Werror on gcc-4.3:

arch/sh/kernel/setup.c: In function 'early_parse_mem':
arch/sh/kernel/setup.c:111: error: format not a string literal and no format arguments
...

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. 2009-03-17T08:49:49+00:00 Paul Mundt lethal@linux-sh.org 2009-03-17T08:49:49+00:00 8263a67e169fdf0d06d172acbf6c03ae172a69d4 This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Add support for SH7786 CPU subtype. 2009-03-03T06:40:25+00:00 Kuninori Morimoto morimoto.kuninori@renesas.com 2009-03-03T06:40:25+00:00 55ba99eb211a06709237cb322ecd8c8b6faf6159 This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This adds preliminary support for the SH7786 CPU subtype.

While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.

More information on this particular CPU subtype is available at:

	http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Only reserve memory under CONFIG_ZERO_PAGE_OFFSET when it != 0. 2009-01-29T02:56:02+00:00 Christopher SMITH chris.smith@st.com 2008-10-06T11:46:18+00:00 48865163109690ed988e2d98d6f258ec743c94c7 Signed-off-by: Chris Smith <chris.smith@st.com> Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Chris Smith <chris.smith@st.com>
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Add support for SH7201 CPU subtype. 2008-12-22T09:43:50+00:00 Peter Griffin pgriffin@mpc-data.co.uk 2008-11-28T13:48:20+00:00 2825999e8a9bd7ab7e25a7e7475c7cdd10371a13 This patch adds support for the SH-2A FPU based SH7201 processor subtype. Signed-off-by: Peter Griffin <pgriffin@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This patch adds support for the SH-2A FPU based SH7201 processor subtype.

Signed-off-by: Peter Griffin <pgriffin@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: add dynamic crash base address support 2008-10-20T02:38:40+00:00 Magnus Damm damm@igel.co.jp 2008-10-09T09:42:55+00:00 4aeaa223433355a281559033f1e7600bfd73238e Add support for dynamic crash kernel base address. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Add support for dynamic crash kernel base address.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Fix up some merge damage. 2008-10-20T02:37:58+00:00 Paul Mundt lethal@linux-sh.org 2008-10-20T02:37:58+00:00 9a19eb2a6607f2f6329efb3c4637fe23afae2cd7 Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Fix debugfs_create_dir's error checking method for arch/sh/kernel/ 2008-10-20T01:40:15+00:00 Zhaolei zhaolei@cn.fujitsu.com 2008-10-17T11:25:03+00:00 9986b311efdc9727a5a48f03c3dac3d536fbaa74 debugfs_create_dir() returns NULL if an error occurs, returns -ENODEV when debugfs is not enabled in the kernel. Signed-off-by: Zhao Lei <zhaolei@cn.fujitsu.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
debugfs_create_dir() returns NULL if an error occurs, returns -ENODEV
when debugfs is not enabled in the kernel.

Signed-off-by: Zhao Lei <zhaolei@cn.fujitsu.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Derive calibrate_delay lpj from clk fwk. 2008-09-08T11:47:42+00:00 Paul Mundt lethal@linux-sh.org 2008-09-08T11:47:42+00:00 cf204fa797cf968de8043491cd469ad0321d0940 All CPUs must have a sensible cpu_clk definition these days, which we can safely use for deriving the preset loops_per_jiffy. The only odd one out is SH-5, which hasn't been hammered in to the framework yet. Based on the ST patch. Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st.com> Signed-off-by: Carl Shaw <carl.shaw@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
All CPUs must have a sensible cpu_clk definition these days, which we can
safely use for deriving the preset loops_per_jiffy. The only odd one out
is SH-5, which hasn't been hammered in to the framework yet.

Based on the ST patch.

Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st.com>
Signed-off-by: Carl Shaw <carl.shaw@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Fix an unusual memory initialisation error. 2008-09-08T01:35:05+00:00 Stuart Menefy stuart.menefy@st.com 2008-09-05T07:29:40+00:00 f040ddaf4cfd28f25ea9d6a42d3c734d5c3f6798 This fixes a problems with the set up of Linux memory: - When reserving memory at boot time, the code previously reserved the bottom page of memory, and then from one page up to the end of the bootmap. This had the desired effect, but was strictly speaking wrong, as the one page was actually whatever CONFIG_ZERO_PAGE_OFFSET had been set to. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This fixes a problems with the set up of Linux memory:

 - When reserving memory at boot time, the code previously reserved
   the bottom page of memory, and then from one page up to the end of
   the bootmap. This had the desired effect, but was strictly speaking
   wrong, as the one page was actually whatever CONFIG_ZERO_PAGE_OFFSET
   had been set to.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>