linux.git/arch/sh/kernel/cpu/sh4, branch v2.6.19

sh: Convert INTC2 to IRQ table registration.

2006-10-20T06:30:55+00:00

Currently the INTC2 code contains a fixed IRQ table that it
iterates through to set the handler type, we move this in to
the CPU subtype setup code instead and allow for submitting
the table that way.

This drops the ST40 tables, as nothing has been happening
with those processors, while converting the only existing
users to use the new table directly (SH7760 and SH7780).

Signed-off-by: Paul Mundt

sh: Fix exception_handling_table alignment.

2006-10-19T07:30:32+00:00

With the recent change ripping out interrupt_table, explicit
padding of the table was missing, causing bad things to happen
when manually inserting handlers in to the table. This problem
particularly showed up in relation to do_fpu_state_restore()
which was inserted quite deeply in to the table and ended up
scribbling over a slab object.

Signed-off-by: Paul Mundt

sh: interrupt exception handling rework

2006-10-12T03:03:04+00:00

Kill off interrupt_table for all of the CPU subtypes, we now
default in to stepping in to do_IRQ() for _all_ IRQ exceptions
and counting the spurious ones, rather than simply flipping on
the ones we cared about. This and enabling the IRQ by default
automatically has already uncovered a couple of bugs and IRQs
that weren't being caught, as well as some that are being
generated far too often (SCI Tx Data Empty, for example).

The general rationale is to use a marker for interrupt exceptions,
test for it in the handle_exception() path, and skip out to
do_IRQ() if it's found. Everything else follows the same behaviour
of finding the cached EXPEVT value in r2/r2_bank, we just rip out
the INTEVT read from entry.S entirely (except for in the kGDB NMI
case, which is another matter).

Note that while this changes the do_IRQ() semantics regarding r4
handling, they were fundamentally broken anyways (relying entirely
on r2_bank for the cached code). With this, we do the INTEVT read
from do_IRQ() itself (in the CONFIG_CPU_HAS_INTEVT case), or fall
back on r4 for the muxed IRQ number, which should also be closer
to what SH-2 and SH-2A want anyways.

Signed-off-by: Paul Mundt

sh: More intelligent entry_mask/way_size calculation.

2006-09-27T09:28:34+00:00

Figure out the cache desc entry_mask at runtime, and remove
hard-coded assumption about the cacheline size.

Signed-off-by: Paul Mundt

sh: Support for L2 cache on newer SH-4A CPUs.

2006-09-27T09:27:43+00:00

This implements preliminary support for the L2 caches found
on newer SH-4A CPUs.

Signed-off-by: Paul Mundt

sh: CPU flags in AT_HWCAP in ELF auxvt.

2006-09-27T09:22:53+00:00

Encode processor flags in AT_HWCAP in the ELF auxiliary vector.

Signed-off-by: Paul Mundt

sh: Add support for SH7706/SH7710/SH7343 CPUs.

2006-09-27T08:38:11+00:00

This adds support for the aforementioned CPU subtypes, and cleans
up some build issues encountered as a result.

Signed-off-by: Paul Mundt

sh: Add setup code for various CPU subtypes.

2006-09-27T08:30:35+00:00

This adds some simple setup code for most of the CPU subtypes,
primarily simple platform device registration.

Signed-off-by: Paul Mundt

sh: Consolidated SH7751/SH7780 PCI support.

2006-09-27T07:43:28+00:00

This cleans up quite a lot of the PCI mess that we
currently have, and attempts to consolidate the
duplication in the SH7780 and SH7751 PCI controllers.

Signed-off-by: Paul Mundt

sh: Store Queue API rework.

2006-09-27T06:49:57+00:00

Rewrite the store queue API for a per-cpu interface in the driver
model. The old miscdevice is dropped, due to TASK_SIZE limitations,
and no one was using it anyways.

Carve up and allocate store queue space with a bitmap, back sq
mapping objects with a slab cache, and let userspace worry about
its own prefetching.

Signed-off-by: Paul Mundt