linux.git/arch/sh/kernel/cpu/init.c, branch v2.6.32 Linux kernel source tree Merge branch 'master' into sh/cachetlb 2009-08-19T00:12:00+00:00 Paul Mundt lethal@linux-sh.org 2009-08-19T00:12:00+00:00 ee8365f23355cdb66e7a6c5c9364e8d3ba4de32f Conflicts: arch/sh/kernel/Makefile_64 
Conflicts:
	arch/sh/kernel/Makefile_64
sh: rework nommu for generic cache.c use. 2009-08-15T00:49:32+00:00 Paul Mundt lethal@linux-sh.org 2009-08-15T00:49:32+00:00 dde5e3ffb770ef2854bbc32c51a365e932919e19 This does a bit of reorganizing for allowing nommu to use the new and generic cache.c, no functional changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This does a bit of reorganizing for allowing nommu to use the new
and generic cache.c, no functional changes.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: delay slot future proofing via EXPMASK on SH-4A parts. 2009-08-14T22:43:21+00:00 Paul Mundt lethal@linux-sh.org 2009-08-14T22:43:21+00:00 7dd6662a92fe9a15ad565045aa60367995cc533d This implements EXPMASK initialization code for SH-4A parts, where it is possible to disable compat features that will go away in newer cores. Presently this includes disabling support for non-nop instructions in the rte delay slot, as well as a sleep instruction being placed in a delay slot (neither of which the kernel does any longer). As a result of this, any future offenders will have illegal slot exceptions generated for them. Associative writes for the memory-mapped cache array are still left enabled, until such a point that special cache operations for SH-4A are provided to move off of the current (and rather dated) SH-4 versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This implements EXPMASK initialization code for SH-4A parts, where it is
possible to disable compat features that will go away in newer cores.
Presently this includes disabling support for non-nop instructions in the
rte delay slot, as well as a sleep instruction being placed in a delay
slot (neither of which the kernel does any longer). As a result of this,
any future offenders will have illegal slot exceptions generated for
them.

Associative writes for the memory-mapped cache array are still left
enabled, until such a point that special cache operations for SH-4A are
provided to move off of the current (and rather dated) SH-4 versions.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: add weak l2_cache_init function. 2009-06-02T03:12:55+00:00 Kuninori Morimoto morimoto.kuninori@renesas.com 2009-06-02T02:49:20+00:00 fab88d9fe98e9091aafeb9789fbf2e04fdace8ed Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Move arch_get_unmapped_area() in to arch/sh/mm/mmap.c. 2008-12-22T09:42:49+00:00 Paul Mundt lethal@linux-sh.org 2008-11-12T04:17:38+00:00 4a4a9be3ebdbf17957d29e3521f328a1145f9431 Now that arch/sh/mm/mmap.c exists, move arch_get_unmapped_area() there. Follows the ARM change. Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Now that arch/sh/mm/mmap.c exists, move arch_get_unmapped_area() there.
Follows the ARM change.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Fix up section mismatches. 2008-03-06T03:43:38+00:00 Paul Mundt lethal@linux-sh.org 2008-03-06T03:43:38+00:00 b2839ed83f54d40870747ac8d655504dff63d1c5 Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Encode L1/L2 cache shape in auxvt. 2008-01-28T04:18:59+00:00 Paul Mundt lethal@linux-sh.org 2007-12-10T06:50:28+00:00 cd01204b82933754a7276838656420477f64d4b8 This adds in the L1I/L1D/L2 cache shape support to their respective entries in the ELF auxvt, based on the Alpha implementation. We use this on the userspace libc side for calculating a tightly packed SHMLBA amongst other things. Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Preparation for uncached jumps through PMB. 2008-01-28T04:18:59+00:00 Stuart Menefy stuart.menefy@st.com 2007-11-30T08:06:36+00:00 cbaa118ecfd99fc5ed7adbd9c34a30e1c05e3c93 Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Disable initial cache flush on SH-5. 2008-01-28T04:18:43+00:00 Paul Mundt lethal@linux-sh.org 2007-11-10T11:25:28+00:00 27a511c6f37c05c5cf8fae9fe513f60d87af9158 Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
sh: Don't reference UBC code in CPU init on sh64. 2008-01-28T04:18:43+00:00 Paul Mundt lethal@linux-sh.org 2007-11-10T11:18:18+00:00 c881cbc033c80d92d1bb7a0446735561a46e1f9c Signed-off-by: Paul Mundt <lethal@linux-sh.org> 
Signed-off-by: Paul Mundt <lethal@linux-sh.org>