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<title>linux.git/arch/riscv/kernel, branch v4.18</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>RISC-V: Fix the rv32i kernel build</title>
<updated>2018-07-04T21:12:53+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2018-07-04T21:12:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=9a6a51154f8be90a76f6a8ea8809115c11cec9dd'/>
<id>9a6a51154f8be90a76f6a8ea8809115c11cec9dd</id>
<content type='text'>
These patches for building 32-bit RISC-V kernel.
 - Fix the compile errors and warnings on RV32I.
 - Fix some incompatible problem on RV32I.
 - Add format.h for compatible of print format.

The fixed width integer types format for Elf_Addr will move to
generic header by another patch. For now, there are some warning
about unexpected argument of type on RV32I.

Change in v1:
 - Fix some error in v1
 - Remove implementation of fixed width integer types format for Elf_Addr.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
These patches for building 32-bit RISC-V kernel.
 - Fix the compile errors and warnings on RV32I.
 - Fix some incompatible problem on RV32I.
 - Add format.h for compatible of print format.

The fixed width integer types format for Elf_Addr will move to
generic header by another patch. For now, there are some warning
about unexpected argument of type on RV32I.

Change in v1:
 - Fix some error in v1
 - Remove implementation of fixed width integer types format for Elf_Addr.
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: Fix PTRACE_SETREGSET bug.</title>
<updated>2018-07-04T21:12:47+00:00</updated>
<author>
<name>Jim Wilson</name>
<email>jimw@sifive.com</email>
</author>
<published>2018-06-11T21:48:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1db9b80980d26fe95c942e0bb8bde2ca715029ad'/>
<id>1db9b80980d26fe95c942e0bb8bde2ca715029ad</id>
<content type='text'>
In riscv_gpr_set, pass regs instead of &amp;regs to user_regset_copyin to fix
gdb segfault.

Signed-off-by: Jim Wilson &lt;jimw@sifive.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
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<pre>
In riscv_gpr_set, pass regs instead of &amp;regs to user_regset_copyin to fix
gdb segfault.

Signed-off-by: Jim Wilson &lt;jimw@sifive.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: Don't include irq-riscv-intc.h</title>
<updated>2018-07-04T21:12:42+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2018-06-22T22:46:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8606544890d7dc4f7a740963f70dc1e1d54f8e30'/>
<id>8606544890d7dc4f7a740963f70dc1e1d54f8e30</id>
<content type='text'>
This file has never existed in the upstream kernel, but it's guarded by
an #ifdef that's also never existed in the upstream kernel.  As a part
of our interrupt controller refactoring this header is no longer
necessary, but this reference managed to sneak in anyway.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This file has never existed in the upstream kernel, but it's guarded by
an #ifdef that's also never existed in the upstream kernel.  As a part
of our interrupt controller refactoring this header is no longer
necessary, but this reference managed to sneak in anyway.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: remove unnecessary of_platform_populate call</title>
<updated>2018-07-04T21:12:38+00:00</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2018-06-19T21:41:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f67f10b8a6c96ab6c1d6946d269e2ca5f9998cc2'/>
<id>f67f10b8a6c96ab6c1d6946d269e2ca5f9998cc2</id>
<content type='text'>
The DT core will call of_platform_default_populate, so it is not
necessary for arch specific code to call it unless there are custom
match entries, auxdata or parent device. Neither of those apply here, so
remove the call.

Cc: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The DT core will call of_platform_default_populate, so it is not
necessary for arch specific code to call it unless there are custom
match entries, auxdata or parent device. Neither of those apply here, so
remove the call.

Cc: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: fix R_RISCV_ADD32/R_RISCV_SUB32 relocations</title>
<updated>2018-07-04T21:12:34+00:00</updated>
<author>
<name>Andreas Schwab</name>
<email>schwab@suse.de</email>
</author>
<published>2018-06-12T17:26:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=781c8fe2da3d2c7c95cd7ffddbab63b80a79da4d'/>
<id>781c8fe2da3d2c7c95cd7ffddbab63b80a79da4d</id>
<content type='text'>
The R_RISCV_ADD32/R_RISCV_SUB32 relocations should add/subtract the
address of the symbol (without overflow check), not its contents.

Signed-off-by: Andreas Schwab &lt;schwab@suse.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The R_RISCV_ADD32/R_RISCV_SUB32 relocations should add/subtract the
address of the symbol (without overflow check), not its contents.

Signed-off-by: Andreas Schwab &lt;schwab@suse.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: Change variable type for 32-bit compatible</title>
<updated>2018-07-04T20:56:52+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong@andestech.com</email>
</author>
<published>2018-06-25T08:49:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7df85002178e708aa749c63020fd333d9f085ced'/>
<id>7df85002178e708aa749c63020fd333d9f085ced</id>
<content type='text'>
Signed-off-by: Zong Li &lt;zong@andestech.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Zong Li &lt;zong@andestech.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux</title>
<updated>2018-06-15T21:42:43+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-06-15T21:42:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6a4d4b3253c1341843ba473429cf76a0e54f053d'/>
<id>6a4d4b3253c1341843ba473429cf76a0e54f053d</id>
<content type='text'>
Pull RISC-V updates from Palmer Dabbelt:
 "This contains some small RISC-V updates I'd like to target for 4.18.

  They are all fairly small this time. Here's a short summary, there's
  more info in the commits/merges:

   - a fix to __clear_user to respect the passed arguments.

   - enough support for the perf subsystem to work with RISC-V's ISA
     defined performance counters.

   - support for sparse and cleanups suggested by it.

   - support for R_RISCV_32 (a relocation, not the 32-bit ISA).

   - some MAINTAINERS cleanups.

   - the addition of CONFIG_HVC_RISCV_SBI to our defconfig, as it's
     always present.

  I've given these a simple build+boot test"

* tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
  RISC-V: Handle R_RISCV_32 in modules
  riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't set
  riscv: add riscv-specific predefines to CHECKFLAGS
  riscv: split the declaration of __copy_user
  riscv: no __user for probe_kernel_address()
  riscv: use NULL instead of a plain 0
  perf: riscv: Add Document for Future Porting Guide
  perf: riscv: preliminary RISC-V support
  MAINTAINERS: Update Albert's email, he's back at Berkeley
  MAINTAINERS: Add myself as a maintainer for SiFive's drivers
  riscv: Fix the bug in memory access fixup code
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull RISC-V updates from Palmer Dabbelt:
 "This contains some small RISC-V updates I'd like to target for 4.18.

  They are all fairly small this time. Here's a short summary, there's
  more info in the commits/merges:

   - a fix to __clear_user to respect the passed arguments.

   - enough support for the perf subsystem to work with RISC-V's ISA
     defined performance counters.

   - support for sparse and cleanups suggested by it.

   - support for R_RISCV_32 (a relocation, not the 32-bit ISA).

   - some MAINTAINERS cleanups.

   - the addition of CONFIG_HVC_RISCV_SBI to our defconfig, as it's
     always present.

  I've given these a simple build+boot test"

* tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
  RISC-V: Handle R_RISCV_32 in modules
  riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't set
  riscv: add riscv-specific predefines to CHECKFLAGS
  riscv: split the declaration of __copy_user
  riscv: no __user for probe_kernel_address()
  riscv: use NULL instead of a plain 0
  perf: riscv: Add Document for Future Porting Guide
  perf: riscv: preliminary RISC-V support
  MAINTAINERS: Update Albert's email, he's back at Berkeley
  MAINTAINERS: Add myself as a maintainer for SiFive's drivers
  riscv: Fix the bug in memory access fixup code
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: Make our port sparse-clean</title>
<updated>2018-06-11T16:09:49+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2018-06-11T16:09:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e0e0c87c022b654bcc79224ce73633f0d274e091'/>
<id>e0e0c87c022b654bcc79224ce73633f0d274e091</id>
<content type='text'>
This patch set contains a handful of fixes that clean up the sparse
results for the RISC-V port.  These patches shouldn't have any
functional difference.  The patches:

* Use NULL instead of 0.
* Clean up __user annotations.
* Split __copy_user into two functions, to make the __user annotations
  valid.

Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch set contains a handful of fixes that clean up the sparse
results for the RISC-V port.  These patches shouldn't have any
functional difference.  The patches:

* Use NULL instead of 0.
* Clean up __user annotations.
* Split __copy_user into two functions, to make the __user annotations
  valid.

Signed-off-by: Palmer Dabbelt &lt;palmer@dabbelt.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: Handle R_RISCV_32 in modules</title>
<updated>2018-06-11T16:04:34+00:00</updated>
<author>
<name>Andreas Schwab</name>
<email>schwab@suse.de</email>
</author>
<published>2018-06-07T10:27:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=77aa85de16aeefd75d639737c7bfcf0d2604e471'/>
<id>77aa85de16aeefd75d639737c7bfcf0d2604e471</id>
<content type='text'>
With CONFIG_MODVERSIONS=y the R_RISCV_32 relocation is used by the
__kcrctab section.

Signed-off-by: Andreas Schwab &lt;schwab@suse.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With CONFIG_MODVERSIONS=y the R_RISCV_32 relocation is used by the
__kcrctab section.

Signed-off-by: Andreas Schwab &lt;schwab@suse.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't set</title>
<updated>2018-06-11T16:04:03+00:00</updated>
<author>
<name>Alan Kao</name>
<email>alankao@andestech.com</email>
</author>
<published>2018-05-08T03:21:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1dd985229d5fc19359250bc0e4235aff217672b2'/>
<id>1dd985229d5fc19359250bc0e4235aff217672b2</id>
<content type='text'>
The EXPORT_SYMBOL(_mcount) for RISC-V ended up inside a
CONFIG_DYNAMIC_FTRACE ifdef.  If you enable modules without enabling
CONFIG_DYNAMIC_FTRACE then you'll get a build error without this patch
because the modules won't be able to find _mcount.

The new behavior is to export _mcount whenever CONFIG_FUNCTION_TRACER is
defined.  This matches what every other architecture is doing.

Signed-off-by: Alan Kao &lt;alankao@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Cc: Zong Li &lt;zong@andestech.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The EXPORT_SYMBOL(_mcount) for RISC-V ended up inside a
CONFIG_DYNAMIC_FTRACE ifdef.  If you enable modules without enabling
CONFIG_DYNAMIC_FTRACE then you'll get a build error without this patch
because the modules won't be able to find _mcount.

The new behavior is to export _mcount whenever CONFIG_FUNCTION_TRACER is
defined.  This matches what every other architecture is doing.

Signed-off-by: Alan Kao &lt;alankao@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Cc: Zong Li &lt;zong@andestech.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
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