linux.git/arch/riscv/kernel/module.c, branch v4.17 Linux kernel source tree RISC-V: Support SUB32 relocation type in kernel module 2018-04-03T03:00:55+00:00 Zong Li zong@andestech.com 2018-03-15T08:50:49+00:00 4aad074c9c1d1302c504e1a26fe434878fe08cd5 Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Support ADD32 relocation type in kernel module 2018-04-03T03:00:55+00:00 Zong Li zong@andestech.com 2018-03-15T08:50:48+00:00 8e691b16769d233f8a8b668dc7fad783459e4573 Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Support ALIGN relocation type in kernel module 2018-04-03T03:00:55+00:00 Zong Li zong@andestech.com 2018-03-15T08:50:47+00:00 29e405cd88c373ddcb3399687311aa869a7c8ee7 Just fail on align type. Kernel modules loader didn't do relax like linker, it is difficult to remove or migrate the code, but the remnant nop instructions harm the performaace of module. We expect the building module with the no-relax option. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
Just fail on align type. Kernel modules loader didn't do relax
like linker, it is difficult to remove or migrate the code,
but the remnant nop instructions harm the performaace of module.
We expect the building module with the no-relax option.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewq 2018-04-03T03:00:55+00:00 Zong Li zong@andestech.com 2018-03-15T08:50:46+00:00 56ea45ae239206d79d776a43bf32cbd8fa4e069d Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module 2018-04-03T03:00:55+00:00 Zong Li zong@andestech.com 2018-03-15T08:50:45+00:00 e7456e696bff09ef2345081bf21e5ce741e2a3ce HI20 and LO12_I/LO12_S relocate the absolute address, the range of offset must in 32-bit. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
HI20 and LO12_I/LO12_S relocate the absolute address, the range of
offset must in 32-bit.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Support CALL relocation type in kernel module 2018-04-03T03:00:54+00:00 Zong Li zong@andestech.com 2018-03-15T08:50:44+00:00 e1910c72bdc405b5028510ccc3ed42f0ed25cc6c Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module 2018-04-03T03:00:54+00:00 Zong Li zong@andestech.com 2018-03-15T08:50:43+00:00 da975dd4818cf42a181910789c096eb6997ed663 For CALL_PLT, emit the plt entry only when offset is more than 32-bit. For PCREL_LO12, it uses the location of corresponding HI20 to get the address of external symbol. It should check the HI20 type is the PCREL_HI20 or GOT_HI20, because sometime the location will have two or more relocation types. For example: 0: 00000797 auipc a5,0x0 0: R_RISCV_ALIGN *ABS* 0: R_RISCV_GOT_HI20 SYMBOL 4: 0007b783 ld a5,0(a5) # 0 <SYMBOL> 4: R_RISCV_PCREL_LO12_I .L0 4: R_RISCV_RELAX *ABS* Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
For CALL_PLT, emit the plt entry only when offset is more than 32-bit.

For PCREL_LO12, it uses the location of corresponding HI20 to
get the address of external symbol. It should check the HI20 type
is the PCREL_HI20 or GOT_HI20, because sometime the location will
have two or more relocation types.
For example:
0:   00000797                auipc   a5,0x0
                     0: R_RISCV_ALIGN        *ABS*
                     0: R_RISCV_GOT_HI20     SYMBOL
4:   0007b783                ld      a5,0(a5) # 0 <SYMBOL>
                     4: R_RISCV_PCREL_LO12_I .L0
                     4: R_RISCV_RELAX        *ABS*

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: User-facing API 2017-09-26T22:26:48+00:00 Palmer Dabbelt palmer@dabbelt.com 2017-07-11T01:07:09+00:00 e2c0cdfba7f69925afc92b20cd9835d81e11a4f1 This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> 
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling.  It also contains some generic code that is ABI visible.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>