linux.git/arch/riscv/kernel/cpu.c, branch v5.19

riscv: Don't output a bogus mmu-type on a no MMU kernel

2022-05-21T19:20:04+00:00

Currently on a 64-bit kernel built without CONFIG_MMU, /proc/cpuinfo will
show the current MMU mode as sv57.

While the device tree property "mmu-type" does have a value "riscv,none" to
describe a CPU without a MMU, since commit 73c7c8f68e72 ("riscv: Use
pgtable_l4_enabled to output mmu_type in cpuinfo"), we no longer rely on
device tree to output the MMU mode. (Not even for CONFIG_32BIT.)

Therefore, instead of readding code to look at the "mmu-type" device tree
property, let's continue with the existing convention to use fixed values
for configurations where we don't determine the MMU mode at runtime.

Add a new fixed value for !CONFIG_MMU in order to output the correct
MMU mode in cpuinfo.

Signed-off-by: Niklas Cassel 
Link: https://lore.kernel.org/r/20220414173037.1381927-1-niklas.cassel@wdc.com
Signed-off-by: Palmer Dabbelt

riscv: add RISC-V Svpbmt extension support

2022-05-12T04:36:33+00:00

Svpbmt (the S should be capitalized) is the
"Supervisor-mode: page-based memory types" extension
that specifies attributes for cacheability, idempotency
and ordering.

The relevant settings are done in special bits in PTEs:

Here is the svpbmt PTE format:
| 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  N     MT     RSW    D   A   G   U   X   W   R   V
        ^

Of the Reserved bits [63:54] in a leaf PTE, the high bit is already
allocated (as the N bit), so bits [62:61] are used as the MT (aka
MemType) field. This field specifies one of three memory types that
are close equivalents (or equivalent in effect) to the three main x86
and ARMv8 memory types - as shown in the following table.

RISC-V
Encoding &
MemType     RISC-V Description
----------  ------------------------------------------------
00 - PMA    Normal Cacheable, No change to implied PMA memory type
01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
11 - Rsvd   Reserved for future standard use

As the extension will not be present on all implementations,
implement a method to handle cpufeatures via alternatives
to not incur runtime penalties on cpu variants not supporting
specific extensions and patch relevant code parts at runtime.

Co-developed-by: Wei Fu 
Signed-off-by: Wei Fu 
Co-developed-by: Liu Shaohua 
Signed-off-by: Liu Shaohua 
Co-developed-by: Guo Ren 
Signed-off-by: Guo Ren 
[moved to use the alternatives mechanism]
Signed-off-by: Heiko Stuebner 
Reviewed-by: Philipp Tomsich 
Link: https://lore.kernel.org/r/20220511192921.2223629-10-heiko@sntech.de
Signed-off-by: Palmer Dabbelt

riscv: cpu.c: don't use kernel-doc markers for comments

2022-03-31T22:42:46+00:00

Repair kernel-doc build warnings caused by using "/**" kernel-doc
markers for comments that are not in kernel-doc format:

cpu.c:89: warning: cannot understand function prototype: 'struct riscv_isa_ext_data isa_ext_arr[] = '
cpu.c:114: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst

Signed-off-by: Randy Dunlap 
Reported-by: kernel test robot 
Reviewed-by: Atish Patra 
Signed-off-by: Palmer Dabbelt

RISC-V: Fix a comment typo in riscv_of_parent_hartid()

2022-03-31T06:22:31+00:00

This fixes a typo in a comment that is both obvious and went unnoticed.

Signed-off-by: Atish Patra 
Fixes: a9b202606c69 ("RISC-V: Improve /proc/cpuinfo output for ISA extensions")
Signed-off-by: Palmer Dabbelt

perf: RISC-V: Add support for SBI PMU and Sscofpmf

2022-03-21T23:07:12+00:00

This series improves perf support for RISC-V based system using SBI PMU
and Sscofpmf extensions, by adding a new generic RISC-V perf framework
along with a pair of drivers: one that usese the new
performance-monitoring extensions and one that keeps support for the
existing systems that only have the legacy counters.

Tested-by: Nikita Shubin 

* palmer/riscv-pmu:
  MAINTAINERS: Add entry for RISC-V PMU drivers
  Documentation: riscv: Remove the old documentation
  RISC-V: Add sscofpmf extension support
  RISC-V: Add perf platform driver based on SBI PMU extension
  RISC-V: Add RISC-V SBI PMU extension definitions
  RISC-V: Add a simple platform driver for RISC-V legacy perf
  RISC-V: Add a perf core library for pmu drivers
  RISC-V: Add CSR encodings for all HPMCOUNTERS
  RISC-V: Remove the current perf implementation

RISC-V: Add sscofpmf extension support

2022-03-21T22:01:09+00:00

The sscofpmf extension allows counter overflow and filtering for
programmable counters. Enable the perf driver to handle the overflow
interrupt. The overflow interrupt is a hart local interrupt.
Thus, per cpu overflow interrupts are setup as a child under the root
INTC irq domain.

Signed-off-by: Atish Patra 
Signed-off-by: Atish Patra 
Signed-off-by: Palmer Dabbelt

RISC-V: Provide a fraemework for RISC-V ISA extensions

2022-03-17T21:09:16+00:00

This series implements a generic framework to parse multi-letter ISA
extensions.

* palmer/riscv-isa:
  RISC-V: Improve /proc/cpuinfo output for ISA extensions
  RISC-V: Do no continue isa string parsing without correct XLEN
  RISC-V: Implement multi-letter ISA extension probing framework
  RISC-V: Extract multi-letter extension names from "riscv, isa"
  RISC-V: Minimal parser for "riscv, isa" strings
  RISC-V: Correctly print supported extensions

RISC-V: Improve /proc/cpuinfo output for ISA extensions

2022-03-17T19:18:12+00:00

Currently, the /proc/cpuinfo outputs the entire riscv,isa string which
is not ideal when we have multiple ISA extensions present in the ISA
string. Some of them may not be enabled in kernel as well.
Same goes for the single letter extensions as well which prints the
entire ISA string. Some of they may not be valid ISA extensions as
well (e.g 'su')

Parse only the valid & enabled ISA extension and print them.

Tested-by: Heiko Stuebner 
Signed-off-by: Atish Patra 
Reviewed-by: Anup Patel 
Signed-off-by: Palmer Dabbelt

riscv: mm: Set sv57 on defaultly

2022-02-15T00:32:45+00:00

This patch sets sv57 on defaultly if CONFIG_64BIT. And do fallback to try
to set sv48 on boot time if sv57 is not supported in current hardware.

Signed-off-by: Qinglin Pan 
Signed-off-by: Palmer Dabbelt

riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo

2022-01-20T01:54:10+00:00

Now that the mmu type is determined at runtime using SATP
characteristic, use the global variable pgtable_l4_enabled to output
mmu type of the processor through /proc/cpuinfo instead of relying on
device tree infos.

Signed-off-by: Alexandre Ghiti 
Reviewed-by: Anup Patel 
Reviewed-by: Palmer Dabbelt 
Signed-off-by: Palmer Dabbelt