linux.git/arch/riscv/kernel/Makefile, branch v5.5

riscv: add nommu support

2019-11-17T23:17:39+00:00

The kernel runs in M-mode without using page tables, and thus can't run
bare metal without help from additional firmware.

Most of the patch is just stubbing out code not needed without page
tables, but there is an interesting detail in the signals implementation:

 - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO
   entry point, but the ELF VDSO is not supported for nommu Linux.
   We instead copy the code to call the syscall onto the stack.

In addition to enabling the nommu code a new defconfig for a small
kernel image that can run in nommu mode on qemu is also provided, to run
a kernel in qemu you can use the following command line:

qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \
	-kernel arch/riscv/boot/loader \
	-drive file=rootfs.ext2,format=raw,id=hd0 \
	-device virtio-blk-device,drive=hd0

Contains contributions from Damien Le Moal .

Signed-off-by: Christoph Hellwig 
Reviewed-by: Anup Patel 
[paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards
 around PCI_IOBASE definition to fix build issues; fixed checkpatch
 issues; move the PCI_IO_* and VMEMMAP address space macros along
 with the others; resolve sparse warning]
Signed-off-by: Paul Walmsley

riscv: provide native clint access for M-mode

2019-11-17T23:17:39+00:00

RISC-V has the concept of a cpu level interrupt controller.  The
interface for it is split between a standardized part that is exposed
as bits in the mstatus/sstatus register and the mie/mip/sie/sip
CRS.  But the bit to actually trigger IPIs is not standardized and
just mentioned as implementable using MMIO.

Add support for IPIs using MMIO using the SiFive clint layout (which
is also shared by Ariane, Kendryte and the Qemu virt platform).
Additionally the MMIO block also supports the time value and timer
compare registers, so they are also set up using the same OF node.
Support for other layouts should also be relatively easy to add in the
future.

Signed-off-by: Christoph Hellwig 
Reviewed-by: Anup Patel 
[paul.walmsley@sifive.com: update include guard format; fix checkpatch
 issues; minor commit message cleanup]
Signed-off-by: Paul Walmsley

riscv: cleanup the default power off implementation

2019-11-13T21:22:52+00:00

Move the sbi poweroff to a separate function and file that is only
compiled if CONFIG_SBI is set.

Signed-off-by: Christoph Hellwig 
Reviewed-by: Anup Patel 
Reviewed-by: Atish Patra 
[paul.walmsley@sifive.com: split the WFI fix into a separate patch]
Signed-off-by: Paul Walmsley

riscv: Add support for perf registers sampling

2019-09-05T07:48:58+00:00

This patch implements the perf registers sampling and validation API
for the riscv arch. The valid registers and their register ID are
defined in perf_regs.h. Perf tool can backtrace in userspace with
unwind library and the registers/user stack dump support.

Signed-off-by: Mao Han 
Cc: Paul Walmsley 
Cc: Greentime Hu 
Cc: Palmer Dabbelt 
Cc: linux-riscv 
Cc: Christoph Hellwig 
Cc: Guo Ren 
Tested-by: Greentime Hu 
[paul.walmsley@sifive.com: minor patch description fix]
Signed-off-by: Paul Walmsley

riscv: Add perf callchain support

2019-09-04T19:43:00+00:00

This patch add support for perf callchain sampling on riscv platforms.
The return address of leaf function is retrieved from pt_regs as
it is not saved in the outmost frame.

Signed-off-by: Mao Han 
Cc: Paul Walmsley 
Cc: Greentime Hu 
Cc: Palmer Dabbelt 
Cc: linux-riscv 
Cc: Christoph Hellwig 
Cc: Guo Ren 
Tested-by: Greentime Hu 
[paul.walmsley@sifive.com: fixed some 'checkpatch.pl --strict' issues;
 fixed patch description spelling]
Signed-off-by: Paul Walmsley

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21T08:50:46+00:00

Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner 
Signed-off-by: Greg Kroah-Hartman

RISC-V: Always compile mm/init.c with cmodel=medany and notrace

2019-03-27T01:25:06+00:00

The Linux RISC-V 32bit kernel is broken after we moved setup_vm() from
kernel/setup.c to mm/init.c because Linux RISC-V 32bit kernel by default
uses cmodel=medlow which results in a non-position-independent setup_vm().

This patch fixes Linux RISC-V 32bit kernel booting by:
1. Forcing cmodel=medany for mm/init.c
2. Moving remaing MM-related stuff va_pa_offset, pfn_base and
   empty_zero_page from kernel/setup.c to mm/init.c

Further, the setup_vm() cannot handle GCC instrumentation for FTRACE so
we disable it for mm/init.c by not using "-pg" compiler flag.

Fixes: 6f1e9e946f0b ("RISC-V: Move setup_vm() to mm/init.c")
Suggested-by: Christoph Hellwig 
Suggested-by: Mike Rapoport 
Signed-off-by: Anup Patel 
Reviewed-by: Mike Rapoport 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

Allow to disable FPU support

2018-10-23T00:02:23+00:00

FPU codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs, so that a no-FPU
configuration is allowed.

Signed-off-by: Alan Kao 
Cc: Greentime Hu 
Cc: Vincent Chen 
Cc: Zong Li 
Cc: Nick Hu 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

Extract FPU context operations from entry.S

2018-10-23T00:02:22+00:00

We move __fstate_save and __fstate_restore to a new source
file, fpu.S.

Signed-off-by: Alan Kao 
Cc: Greentime Hu 
Cc: Vincent Chen 
Cc: Zong Li 
Cc: Nick Hu 
Reviewed-by: Christoph Hellwig 
Signed-off-by: Palmer Dabbelt

perf: riscv: preliminary RISC-V support

2018-06-04T21:02:01+00:00

This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles.  Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.

riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec.  Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes.  Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.

Cc: Nick Hu 
Cc: Greentime Hu 
Signed-off-by: Alan Kao 
Signed-off-by: Palmer Dabbelt