linux.git/arch/riscv/include/asm/vector.h, branch v6.5

RISC-V: vector: export VLENB csr in __sc_riscv_v_state

2023-08-22T20:55:12+00:00

VLENB is critical for callers of ptrace to reconstruct Vector register
files from the register dump of NT_RISCV_VECTOR. Also, future systems
may will have a writable VLENB, so add it now to potentially save future
compatibility issue.

Fixes: 0c59922c769a ("riscv: Add ptrace vector support")
Signed-off-by: Andy Chiu 
Link: https://lore.kernel.org/r/20230816155450.26200-3-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt

riscv: Discard vector state on syscalls

2023-07-04T15:59:24+00:00

The RISC-V vector specification states:
  Executing a system call causes all caller-saved vector registers
  (v0-v31, vl, vtype) and vstart to become unspecified.

The vector registers are set to all 1s, vill is set (invalid), and the
vector status is set to Dirty.

That way we can prevent userspace from accidentally relying on the
stated save.

Rémi pointed out [1] that writing to the registers might be
superfluous, and setting vill is sufficient.

Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@basile.remlab.net/ # [1]
Suggested-by: Darius Rad 
Suggested-by: Palmer Dabbelt 
Suggested-by: Rémi Denis-Courmont 
Signed-off-by: Björn Töpel 
Link: https://lore.kernel.org/r/20230629142228.1125715-1-bjorn@kernel.org
Signed-off-by: Palmer Dabbelt

riscv: Add prctl controls for userspace vector management

2023-06-08T14:16:53+00:00

This patch add two riscv-specific prctls, to allow usespace control the
use of vector unit:

 * PR_RISCV_V_SET_CONTROL: control the permission to use Vector at next,
   or all following execve for a thread. Turning off a thread's Vector
   live is not possible since libraries may have registered ifunc that
   may execute Vector instructions.
 * PR_RISCV_V_GET_CONTROL: get the same permission setting for the
   current thread, and the setting for following execve(s).

Signed-off-by: Andy Chiu 
Reviewed-by: Greentime Hu 
Reviewed-by: Vincent Chen 
Link: https://lore.kernel.org/r/20230605110724.21391-22-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt

riscv: Allocate user's vector context in the first-use trap

2023-06-08T14:16:44+00:00

Vector unit is disabled by default for all user processes. Thus, a
process will take a trap (illegal instruction) into kernel at the first
time when it uses Vector. Only after then, the kernel allocates V
context and starts take care of the context for that user process.

Suggested-by: Richard Henderson 
Link: https://lore.kernel.org/r/3923eeee-e4dc-0911-40bf-84c34aee962d@linaro.org
Signed-off-by: Andy Chiu 
Reviewed-by: Conor Dooley 
Link: https://lore.kernel.org/r/20230605110724.21391-12-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt

riscv: Add task switch support for vector

2023-06-08T14:16:43+00:00

This patch adds task switch support for vector. It also supports all
lengths of vlen.

Suggested-by: Andrew Waterman 
Co-developed-by: Nick Knight 
Signed-off-by: Nick Knight 
Co-developed-by: Guo Ren 
Signed-off-by: Guo Ren 
Co-developed-by: Vincent Chen 
Signed-off-by: Vincent Chen 
Co-developed-by: Ruinland Tsai 
Signed-off-by: Ruinland Tsai 
Signed-off-by: Greentime Hu 
Signed-off-by: Vineet Gupta 
Signed-off-by: Andy Chiu 
Reviewed-by: Conor Dooley 
Reviewed-by: Björn Töpel 
Reviewed-by: Heiko Stuebner 
Tested-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20230605110724.21391-11-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt

riscv: Introduce struct/helpers to save/restore per-task Vector state

2023-06-08T14:16:42+00:00

Add vector state context struct to be added later in thread_struct. And
prepare low-level helper functions to save/restore vector contexts.

This include Vector Regfile and CSRs holding dynamic configuration state
(vstart, vl, vtype, vcsr). The Vec Register width could be implementation
defined, but same for all processes, so that is saved separately.

This is not yet wired into final thread_struct - will be done when
__switch_to actually starts doing this in later patches.

Given the variable (and potentially large) size of regfile, they are
saved in dynamically allocated memory, pointed to by datap pointer in
__riscv_v_ext_state.

Co-developed-by: Vincent Chen 
Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
Signed-off-by: Vineet Gupta 
Signed-off-by: Andy Chiu 
Acked-by: Conor Dooley 
Reviewed-by: Guo Ren 
Reviewed-by: Björn Töpel 
Reviewed-by: Heiko Stuebner 
Tested-by: Heiko Stuebner 
Reviewed-by: Palmer Dabbelt 
Link: https://lore.kernel.org/r/20230605110724.21391-10-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt

riscv: Introduce riscv_v_vsize to record size of Vector context

2023-06-08T14:16:41+00:00

This patch is used to detect the size of CPU vector registers and use
riscv_v_vsize to save the size of all the vector registers. It assumes all
harts has the same capabilities in a SMP system. If a core detects VLENB
that is different from the boot core, then it warns and turns off V
support for user space.

Co-developed-by: Guo Ren 
Signed-off-by: Guo Ren 
Co-developed-by: Vincent Chen 
Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
Signed-off-by: Andy Chiu 
Reviewed-by: Conor Dooley 
Reviewed-by: Heiko Stuebner 
Tested-by: Heiko Stuebner 
Reviewed-by: Palmer Dabbelt 
Link: https://lore.kernel.org/r/20230605110724.21391-9-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt

riscv: Introduce Vector enable/disable helpers

2023-06-08T14:16:40+00:00

These are small and likely to be frequently called so implement as
inline routines (vs. function call).

Co-developed-by: Guo Ren 
Signed-off-by: Guo Ren 
Co-developed-by: Vincent Chen 
Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
Signed-off-by: Vineet Gupta 
Signed-off-by: Andy Chiu 
Reviewed-by: Conor Dooley 
Reviewed-by: Heiko Stuebner 
Tested-by: Heiko Stuebner 
Reviewed-by: Palmer Dabbelt 
Link: https://lore.kernel.org/r/20230605110724.21391-8-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt

riscv: Extending cpufeature.c to detect V-extension

2023-06-08T14:16:35+00:00

Add V-extension into riscv_isa_ext_keys array and detect it with isa
string parsing.

Signed-off-by: Guo Ren 
Signed-off-by: Guo Ren 
Signed-off-by: Greentime Hu 
Suggested-by: Vineet Gupta 
Co-developed-by: Andy Chiu 
Signed-off-by: Andy Chiu 
Reviewed-by: Conor Dooley 
Reviewed-by: Heiko Stuebner 
Tested-by: Heiko Stuebner 
Reviewed-by: Palmer Dabbelt 
Link: https://lore.kernel.org/r/20230605110724.21391-3-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt