linux.git/arch/riscv/boot, branch v6.5

Merge tag 'riscv-dt-for-v6.5-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

2023-06-20T21:06:54+00:00

RISC-V Devicetrees for v6.5 Part 2

T-Head:
Add a basic dtsi, Kconfig bits & trivial binding additions for the T-Head
1520 SoC (codename "light"). This SoC can be found on the Lichee Pi 4a,
for which a minimal dts is added.

Misc:
Re-sort the dts Makefile to be in alphanumerical order by directory.

Signed-off-by: Conor Dooley 

* tag 'riscv-dt-for-v6.5-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: sort makefile entries by directory
  riscv: defconfig: enable T-HEAD SoC
  MAINTAINERS: add entry for T-HEAD RISC-V SoC
  riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
  riscv: dts: add initial T-HEAD TH1520 SoC device tree
  riscv: Add the T-HEAD SoC family Kconfig option
  dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
  dt-bindings: timer: Add T-HEAD TH1520 clint
  dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC

Link: https://lore.kernel.org/r/20230620-fidelity-variety-60b47c889e31@spud
Signed-off-by: Arnd Bergmann

Merge tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

2023-06-20T20:49:35+00:00

RISC-V Devicetrees for v6.5

StarFive:
Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P
being power, support for the JH7110. PMIC and frequency scaling support
for the JH7110 equipped VisionFive 2.
Most of the DT bits for the JH7110, and the SBCs using it, are pending
support for one of the clock controllers, so it's a smaller set of
changes than I would have hoped for.

Misc:
Pick up some dt-binding cleanup that Palmer assigned to me & had no
uptake from the respective maintainers. My powers of estimation failed
me again, with part of my motivation for picking them up being the
addition of new platforms that ended up not making it. Hopefully next
window for those, as they were relatively close.
Exclude the Allwinner and Renesas subdirectories from the Misc.
MAINTAINERS entry, since I do not take care of those.

Signed-off-by: Conor Dooley 

* tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Add cpu scaling for JH7110 SoC
  riscv: dts: starfive: Enable axp15060 pmic for cpufreq
  dt-bindings: interrupt-controller: sifive,plic: Sort compatible values
  dt-bindings: timer: sifive,clint: Clean up compatible value section
  riscv: dts: starfive: jh7110: Add watchdog node
  riscv: dts: starfive: jh7100: Add watchdog node
  riscv: dts: starfive: Add PMU controller node
  MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry

Link: https://lore.kernel.org/r/20230612-fasting-floss-0bc05a08bc7a@spud
Signed-off-by: Arnd Bergmann

riscv: dts: sort makefile entries by directory

2023-06-19T06:59:36+00:00

New additions to the list have tried to respect alphanumeric ordering,
but the thing was out of order to start with. Sort it.

Signed-off-by: Conor Dooley

Merge patch series "Add Sipeed Lichee Pi 4A RISC-V board support"

2023-06-17T18:19:21+00:00

Jisheng Zhang  says:

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.

This also pulls in -rc2, because of some maintainers re-jigging that
went on in the interim in commit 80e62bc8487b ("MAINTAINERS: re-sort
all entries and fields").

Link: https://lore.kernel.org/r/20230617161529.2092-1-jszhang@kernel.org
Signed-off-by: Conor Dooley

riscv: dts: thead: add sipeed Lichee Pi 4A board device tree

2023-06-17T18:04:08+00:00

Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.

Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.

Signed-off-by: Jisheng Zhang 
Signed-off-by: Conor Dooley

riscv: dts: add initial T-HEAD TH1520 SoC device tree

2023-06-17T18:04:08+00:00

Add initial device tree for the TH1520 RISC-V SoC by T-HEAD.

Signed-off-by: Jisheng Zhang 
Signed-off-by: Conor Dooley

riscv: dts: starfive: Add cpu scaling for JH7110 SoC

2023-06-06T11:32:06+00:00

Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.

Signed-off-by: Mason Huo 
Signed-off-by: Conor Dooley

riscv: dts: starfive: Enable axp15060 pmic for cpufreq

2023-06-06T11:32:06+00:00

The VisionFive 2 board has an embedded pmic axp15060,
which supports the cpu DVFS through the dcdc2 regulator.
This patch enables axp15060 pmic and configs the dcdc2.

Signed-off-by: Mason Huo 
Signed-off-by: Conor Dooley

riscv: dts: allwinner: d1: Add SPI controllers node

2023-05-18T21:12:16+00:00

Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have
an optional SPI flash that connects to the SPI0 controller.

This controller is the same for R329/D1/R528/T113s SoCs and
should be supported by the sun50i-r329-spi driver.

So let's add its DT nodes.

Signed-off-by: Maksim Kiselev 
Acked-by: Conor Dooley 
Reviewed-by: Andre Przywara 
Reviewed-by: Jernej Skrabec 
Link: https://lore.kernel.org/r/20230510081121.3463710-6-bigunclemax@gmail.com
Signed-off-by: Jernej Skrabec

riscv: dts: starfive: jh7110: Add watchdog node

2023-05-15T16:44:38+00:00

Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu 
Reviewed-by: Walker Chen 
Signed-off-by: Conor Dooley