linux.git/arch/riscv/boot, branch v6.16 Linux kernel source tree Merge tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2025-05-31T15:14:37+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-05-31T15:14:37+00:00 31848987f177a6c0944fd0254a55ffd7c52a8c50 Pull sophgo SoC devicetree updates from Arnd Bergmann: "The Sophgo SG2044 SoC is their second generation server chip with 64 cores, following the SG2042. In addition, there are minor updates for the cv180x SoCs" * tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10 dt-bindings: riscv: sophgo: Add SG2044 compatible string dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi riscv: dts: sophgo: Move riscv cpu definition to a separate file riscv: dts: sophgo: Move all soc specific device into soc dtsi file riscv: sophgo: dts: Add spi controller for SG2042 riscv: dts: sophgo: sg2042: add pinctrl support 
Pull sophgo SoC devicetree updates from Arnd Bergmann:
 "The Sophgo SG2044 SoC is their second generation server chip with 64
  cores, following the SG2042.

  In addition, there are minor updates for the cv180x SoCs"

* tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
  riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
  dt-bindings: riscv: sophgo: Add SG2044 compatible string
  dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
  dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
  riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
  riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
  riscv: dts: sophgo: Move riscv cpu definition to a separate file
  riscv: dts: sophgo: Move all soc specific device into soc dtsi file
  riscv: sophgo: dts: Add spi controller for SG2042
  riscv: dts: sophgo: sg2042: add pinctrl support
Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2025-05-31T15:08:56+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-05-31T15:08:56+00:00 ec71f661a572a770d7c861cd52a50cbbb0e1a8d1 Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ... 
Pull SoC devicetree updates from Arnd Bergmann:
 "There are 11 newly supported SoCs, but these are all either new
  variants of existing designs, or straight reuses of the existing chip
  in a new package:

   - RK3562 is a new chip based on the old Cortex-A53 core, apparently a
     low-cost version of the Cortex-A55 based RK3568/RK3566.

   - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
     set of on-chip peripherals.

   - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2
     family

   - Amlogic S6/S7/S7D

   - Samsung Exynos7870 is an older chip similar to Exynos7885

   - WonderMedia wm8950 is a minor variation on the wm8850 chip

   - Amlogic s805y is almost idential to s805x

   - Allwinner A523 is similar to A527 and T527

   - Qualcomm MSM8926 is a variant of MSM8226

   - Qualcomm Snapdragon X1P42100 is related to R1E80100

  There are also 65 boards, including reference designs for the chips
  above, this includes

   - 12 new boards based on TI K3 series chips, most of them from
     Toradex

   - 10 devices using Rockchips RK35xx and PX30 chips

   - 2 phones and 2 laptops based on Qualcomm Snapdragon designs

   - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses

   - 3 Samsung Galaxy phones based on Exynos7870

   - 5 Allwinner based boards using a variety of ARMv8 chips

   - 9 32-bit machines, each based on a different SoC family

  Aside from the new hardware, there is the usual set of cleanups and
  newly added hardware support on existing machines, for a total of 965
  devicetree changesets"

* tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits)
  MAINTAINERS, mailmap: update Sven Peter's email address
  arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
  arm64: dts: nuvoton: Add pinctrl
  ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
  arm64: dts: blaize-blzp1600: Enable GPIO support
  dt-bindings: clock: socfpga: convert to yaml
  arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3562 pcie unit addresses
  arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
  arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
  arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3576 pcie unit addresses
  arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
  arm64: dts: rockchip: Add missing SFC power-domains to rk3576
  Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
  arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
  arm64: dts: mt6359: Rename RTC node to match binding expectations
  arm64: dts: mt8365-evk: Add goodix touchscreen support
  arm64: dts: mediatek: mt8188: Add missing #reset-cells property
  arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
  ...
Merge tag 'renesas-dts-for-v6.16-tag3' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt 2025-05-21T21:59:56+00:00 Arnd Bergmann arnd@arndb.de 2025-05-21T21:59:55+00:00 17e6320b0d0f435f0d136602218b7815043d589e Renesas DTS updates for v6.16 (take three) - Silence a DTC warning, - Add an extra compatible value to avoid future issues. * tag 'renesas-dts-for-v6.16-tag3' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: riscv: dts: renesas: Add specific RZ/Five cache compatible arm64: dts: renesas: sparrow-hawk: Disable dtc spi_bus_bridge check Link: https://lore.kernel.org/r/cover.1747399860.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
Renesas DTS updates for v6.16 (take three)

  - Silence a DTC warning,
  - Add an extra compatible value to avoid future issues.

* tag 'renesas-dts-for-v6.16-tag3' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  riscv: dts: renesas: Add specific RZ/Five cache compatible
  arm64: dts: renesas: sparrow-hawk: Disable dtc spi_bus_bridge check

Link: https://lore.kernel.org/r/cover.1747399860.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt 2025-05-21T21:57:49+00:00 Arnd Bergmann arnd@arndb.de 2025-05-21T21:57:48+00:00 00000994fe32264d45e4e011d258779bfb26f6b0 RISC-V Devicetrees for v6.16 Starfive: All Starfive this time (again), enabling the usb3 port on the framework laptop mainboard, and a few cleanup patches that are syncing things with the dts used by U-Boot. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader riscv: dts: starfive: jh7110-common: add eeprom node to i2c5 riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg riscv: dts: starfive: jh7110-common: use macros for MMC0 pins riscv: dts: starfive: fml13v01: enable USB 3.0 port Link: https://lore.kernel.org/r/20250516-gap-exploring-f8f516ab4e1c@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
RISC-V Devicetrees for v6.16

Starfive:
All Starfive this time (again), enabling the usb3 port on the framework
laptop mainboard, and a few cleanup patches that are syncing things with
the dts used by U-Boot.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
  riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
  riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
  riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
  riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
  riscv: dts: starfive: fml13v01: enable USB 3.0 port

Link: https://lore.kernel.org/r/20250516-gap-exploring-f8f516ab4e1c@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux into soc/dt 2025-05-21T21:48:03+00:00 Arnd Bergmann arnd@arndb.de 2025-05-21T21:48:02+00:00 ba32d96e90c113b8aa1b362c4cbb10a6bd1be62c RISC-V SpacemiT DT changes for 6.16 - Add clock driver, fix for pinctrl/uart - Add gpio support, enable LED heartbeat * tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: add gpio LED for system heartbeat riscv: dts: spacemit: add gpio support for K1 SoC riscv: dts: spacemit: Acquire clocks for UART riscv: dts: spacemit: Acquire clocks for pinctrl riscv: dts: spacemit: Add clock tree for SpacemiT K1 dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
RISC-V SpacemiT DT changes for 6.16

- Add clock driver, fix for pinctrl/uart
- Add gpio support, enable LED heartbeat

* tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux:
  riscv: dts: spacemit: add gpio LED for system heartbeat
  riscv: dts: spacemit: add gpio support for K1 SoC
  riscv: dts: spacemit: Acquire clocks for UART
  riscv: dts: spacemit: Acquire clocks for pinctrl
  riscv: dts: spacemit: Add clock tree for SpacemiT K1
  dt-bindings: clock: spacemit: Add spacemit,k1-pll
  dt-bindings: soc: spacemit: Add spacemit,k1-syscon

Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX 2025-05-18T22:23:26+00:00 Inochi Amaoto inochiama@gmail.com 2025-05-04T10:45:52+00:00 108a76779829a5e8001b1051080aaa93e7fc02ea replace newly added precise compatible with old one for existed clock device of CV18XX series SoCs. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250504104553.1447819-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> 
replace newly added precise compatible with old one for existed
clock device of CV18XX series SoCs.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250504104553.1447819-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10 2025-05-18T22:23:26+00:00 Inochi Amaoto inochiama@gmail.com 2025-04-13T22:35:04+00:00 ae5bac370ed40ce09d4d0f35e7149f4dc6ec893f Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC. This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port, 1 microSD slot. Add initial device tree of this board with uart support. Link: https://lore.kernel.org/r/20250413223507.46480-11-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> 
Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC.
This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port,
1 microSD slot.

Add initial device tree of this board with uart support.

Link: https://lore.kernel.org/r/20250413223507.46480-11-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number 2025-05-18T22:23:26+00:00 Inochi Amaoto inochiama@gmail.com 2025-04-30T01:26:53+00:00 e595fa85dbd2618c4ed51a5e3186111356fa499d Since riscv and arm architecture use different interrupt definitions, use a macro SOC_PERIPHERAL_IRQ mask this difference. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250430012654.235830-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> 
Since riscv and arm architecture use different interrupt definitions,
use a macro SOC_PERIPHERAL_IRQ mask this difference.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi 2025-05-18T22:23:26+00:00 Inochi Amaoto inochiama@gmail.com 2025-04-30T01:26:52+00:00 a0cd6d17f8c8c3b47e8930e47de81e5af3c30f5c As the cv18xx.dtsi serves as a common peripheral header for all riscv cv180x/cv181x/sg200x SoCs, it not cover the entire cv18xx series as there is cv182x and cv183x. So rename the header file to make it precise. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250430012654.235830-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> 
As the cv18xx.dtsi serves as a common peripheral header for all
riscv cv180x/cv181x/sg200x SoCs, it not cover the entire cv18xx
series as there is cv182x and cv183x. So rename the header file
to make it precise.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
riscv: dts: sophgo: Move riscv cpu definition to a separate file 2025-05-18T22:23:26+00:00 Inochi Amaoto inochiama@gmail.com 2025-04-30T01:26:51+00:00 0212bd4fadbd30b2eb9982deab5e74f2fdff9bff As sg2000 and sg2002 can boot from an arm a53 core, it is not suitable to left the riscv cpu definition in the common peripheral header. Move the riscv related device into a separate header file, so the arm subsystem can reuse the common peripheral header. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250430012654.235830-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> 
As sg2000 and sg2002 can boot from an arm a53 core, it is not
suitable to left the riscv cpu definition in the common peripheral
header.

Move the riscv related device into a separate header file, so the
arm subsystem can reuse the common peripheral header.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>